{"id":"https://openalex.org/W4225364135","doi":"https://doi.org/10.1109/mm.2022.3163132","title":"Vector Runahead for Indirect Memory Accesses","display_name":"Vector Runahead for Indirect Memory Accesses","publication_year":2022,"publication_date":"2022-03-29","ids":{"openalex":"https://openalex.org/W4225364135","doi":"https://doi.org/10.1109/mm.2022.3163132"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2022.3163132","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2022.3163132","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://www.research.ed.ac.uk/en/publications/46a06654-ff9a-4ad3-9e25-f2a7d1a2b45f","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043018563","display_name":"Ajeya Naithani","orcid":"https://orcid.org/0000-0002-8291-4230"},"institutions":[{"id":"https://openalex.org/I2801227569","display_name":"Ghent University Hospital","ror":"https://ror.org/00xmkp704","country_code":"BE","type":"healthcare","lineage":["https://openalex.org/I2801227569"]}],"countries":["BE"],"is_corresponding":true,"raw_author_name":"Ajeya Naithani","raw_affiliation_strings":["Ghent University, Ghent, Belgium"],"affiliations":[{"raw_affiliation_string":"Ghent University, Ghent, Belgium","institution_ids":["https://openalex.org/I2801227569"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041446247","display_name":"Sam Ainsworth","orcid":"https://orcid.org/0000-0002-3726-0055"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Sam Ainsworth","raw_affiliation_strings":["University of Edinburgh, Edinburgh, U.K"],"affiliations":[{"raw_affiliation_string":"University of Edinburgh, Edinburgh, U.K","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047443783","display_name":"Timothy M. Jones","orcid":"https://orcid.org/0000-0002-4114-7661"},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Timothy M. Jones","raw_affiliation_strings":["University of Cambridge, Cambridge, U.K"],"affiliations":[{"raw_affiliation_string":"University of Cambridge, Cambridge, U.K","institution_ids":["https://openalex.org/I241749"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033119975","display_name":"Lieven Eeckhout","orcid":"https://orcid.org/0000-0001-8792-4473"},"institutions":[{"id":"https://openalex.org/I2801227569","display_name":"Ghent University Hospital","ror":"https://ror.org/00xmkp704","country_code":"BE","type":"healthcare","lineage":["https://openalex.org/I2801227569"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Lieven Eeckhout","raw_affiliation_strings":["Ghent University, Ghent, Belgium"],"affiliations":[{"raw_affiliation_string":"Ghent University, Ghent, Belgium","institution_ids":["https://openalex.org/I2801227569"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5043018563"],"corresponding_institution_ids":["https://openalex.org/I2801227569"],"apc_list":null,"apc_paid":null,"fwci":0.4666,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.57900413,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"42","issue":"4","first_page":"116","last_page":"123"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9134931564331055},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.73455411195755},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.6847065687179565},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.6285461187362671},{"id":"https://openalex.org/keywords/data-parallelism","display_name":"Data parallelism","score":0.5386279821395874},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.5188023447990417},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4200182259082794},{"id":"https://openalex.org/keywords/speculative-multithreading","display_name":"Speculative multithreading","score":0.41703659296035767},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.329677015542984},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1999276876449585},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.1973164975643158},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16465923190116882},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.09304362535476685},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.08142286539077759}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9134931564331055},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.73455411195755},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.6847065687179565},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.6285461187362671},{"id":"https://openalex.org/C61483411","wikidata":"https://www.wikidata.org/wiki/Q3124522","display_name":"Data parallelism","level":3,"score":0.5386279821395874},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.5188023447990417},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4200182259082794},{"id":"https://openalex.org/C15296174","wikidata":"https://www.wikidata.org/wiki/Q7575343","display_name":"Speculative multithreading","level":4,"score":0.41703659296035767},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.329677015542984},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1999276876449585},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.1973164975643158},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16465923190116882},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.09304362535476685},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.08142286539077759}],"mesh":[],"locations_count":6,"locations":[{"id":"doi:10.1109/mm.2022.3163132","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2022.3163132","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},{"id":"pmh:oai:pure.ed.ac.uk:openaire/46a06654-ff9a-4ad3-9e25-f2a7d1a2b45f","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/46a06654-ff9a-4ad3-9e25-f2a7d1a2b45f","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Naithani, A, Ainsworth, S, Jones, T & Eeckhout, L 2022, 'Vector Runahead for Indirect Memory Accesses', IEEE Micro, vol. 42, no. 4, pp. 116-123. https://doi.org/10.1109/MM.2022.3163132","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:archive.ugent.be:8764676","is_oa":true,"landing_page_url":"http://hdl.handle.net/1854/LU-8764676","pdf_url":null,"source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN: 1937-4143","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:pure.ed.ac.uk:publications/46a06654-ff9a-4ad3-9e25-f2a7d1a2b45f","is_oa":false,"landing_page_url":"http://hdl.handle.net/20.500.11820/46a06654-ff9a-4ad3-9e25-f2a7d1a2b45f","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""},{"id":"pmh:oai:www.repository.cam.ac.uk:1810/354271","is_oa":true,"landing_page_url":"https://www.repository.cam.ac.uk/handle/1810/354271","pdf_url":null,"source":{"id":"https://openalex.org/S4306401777","display_name":"Apollo (University of Cambridge)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I241749","host_organization_name":"University of Cambridge","host_organization_lineage":["https://openalex.org/I241749"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},{"id":"doi:10.17863/cam.100138","is_oa":true,"landing_page_url":"https://doi.org/10.17863/cam.100138","pdf_url":null,"source":{"id":"https://openalex.org/S7407050737","display_name":"Apollo","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article-journal"}],"best_oa_location":{"id":"pmh:oai:pure.ed.ac.uk:openaire/46a06654-ff9a-4ad3-9e25-f2a7d1a2b45f","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/46a06654-ff9a-4ad3-9e25-f2a7d1a2b45f","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Naithani, A, Ainsworth, S, Jones, T & Eeckhout, L 2022, 'Vector Runahead for Indirect Memory Accesses', IEEE Micro, vol. 42, no. 4, pp. 116-123. https://doi.org/10.1109/MM.2022.3163132","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G256726586","display_name":null,"funder_award_id":"EP/P020011/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G3782881470","display_name":null,"funder_award_id":"741097","funder_id":"https://openalex.org/F4320338335","funder_display_name":"H2020 European Research Council"},{"id":"https://openalex.org/G4941156546","display_name":null,"funder_award_id":"EP/W00576X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5765668298","display_name":null,"funder_award_id":"G.0144.17N","funder_id":"https://openalex.org/F4320321730","funder_display_name":"Fonds Wetenschappelijk Onderzoek"},{"id":"https://openalex.org/G6886552787","display_name":"Automatic Binary Parallelisation","funder_award_id":"EP/P020011/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320321730","display_name":"Fonds Wetenschappelijk Onderzoek","ror":"https://ror.org/03qtxy027"},{"id":"https://openalex.org/F4320322603","display_name":"Universiteit Gent","ror":"https://ror.org/00cv9y106"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"},{"id":"https://openalex.org/F4320338335","display_name":"H2020 European Research Council","ror":"https://ror.org/0472cxd90"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2107354725","https://openalex.org/W2121082877","https://openalex.org/W2123608497","https://openalex.org/W2154001575","https://openalex.org/W2234355962","https://openalex.org/W2791260415","https://openalex.org/W2941917372","https://openalex.org/W2963311060","https://openalex.org/W3012303953","https://openalex.org/W3016777042","https://openalex.org/W3187569413","https://openalex.org/W4232120412","https://openalex.org/W6678286823"],"related_works":["https://openalex.org/W4240606930","https://openalex.org/W2526302199","https://openalex.org/W2003935582","https://openalex.org/W2950520577","https://openalex.org/W4247496551","https://openalex.org/W3007272028","https://openalex.org/W2105992728","https://openalex.org/W2020784655","https://openalex.org/W2082701182","https://openalex.org/W2126220043"],"abstract_inverted_index":{"Vector":[0],"runahead":[1,22,36,56],"delivers":[2],"extremely":[3],"high":[4],"memory-level":[5,53],"parallelism":[6,54],"even":[7],"for":[8,73],"the":[9],"chains":[10],"of":[11,50],"dependent":[12],"memory":[13],"accesses":[14],"with":[15],"complex":[16],"intermediate":[17],"address":[18],"computation,":[19],"which":[20,63],"conventional":[21],"techniques":[23],"fundamentally":[24],"cannot":[25],"handle":[26],"and,":[27],"therefore,":[28],"have":[29],"ignored.":[30],"It":[31],"does":[32],"this":[33],"by":[34],"rearchitecting":[35],"to":[37],"use":[38],"speculative":[39],"data-level":[40],"parallelism,":[41],"rather":[42],"than":[43,58],"work":[44],"skipping,":[45],"as":[46],"its":[47],"primary":[48],"form":[49],"extracting":[51],"more":[52],"in":[55],"mode":[57],"a":[59],"true":[60],"execution":[61],"can,":[62],"we":[64],"hope":[65],"will":[66],"bring":[67],"about":[68],"an":[69],"entirely":[70],"new":[71],"dimension":[72],"high-performance":[74],"processors.":[75]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-04-03T22:45:19.894376","created_date":"2025-10-10T00:00:00"}
