{"id":"https://openalex.org/W4210384431","doi":"https://doi.org/10.1109/mm.2021.3137536","title":"Special Issue on In-Memory Computing","display_name":"Special Issue on In-Memory Computing","publication_year":2022,"publication_date":"2022-01-01","ids":{"openalex":"https://openalex.org/W4210384431","doi":"https://doi.org/10.1109/mm.2021.3137536"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2021.3137536","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mm.2021.3137536","pdf_url":"https://ieeexplore.ieee.org/ielx7/40/9705173/09705183.pdf","source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://ieeexplore.ieee.org/ielx7/40/9705173/09705183.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027544576","display_name":"Reetuparna Das","orcid":"https://orcid.org/0000-0002-5894-8342"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Reetuparna Das","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA"],"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5027544576"],"corresponding_institution_ids":["https://openalex.org/I27837315"],"apc_list":null,"apc_paid":null,"fwci":0.0915,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.36841583,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"42","issue":"1","first_page":"87","last_page":"88"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9372000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.87461256980896},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.7060112953186035},{"id":"https://openalex.org/keywords/in-memory-processing","display_name":"In-Memory Processing","score":0.5746726393699646},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.5466861724853516},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5241432785987854},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5048642754554749},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.4835895895957947},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.4628450572490692},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4626534581184387},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.45137137174606323},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4433205723762512},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.4264872074127197},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4129411578178406},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.41206037998199463},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30835598707199097},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.2754303514957428},{"id":"https://openalex.org/keywords/search-engine","display_name":"Search engine","score":0.08023375272750854}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.87461256980896},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.7060112953186035},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.5746726393699646},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.5466861724853516},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5241432785987854},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5048642754554749},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.4835895895957947},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.4628450572490692},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4626534581184387},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.45137137174606323},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4433205723762512},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.4264872074127197},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4129411578178406},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.41206037998199463},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30835598707199097},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.2754303514957428},{"id":"https://openalex.org/C97854310","wikidata":"https://www.wikidata.org/wiki/Q19541","display_name":"Search engine","level":2,"score":0.08023375272750854},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0},{"id":"https://openalex.org/C194222762","wikidata":"https://www.wikidata.org/wiki/Q114486","display_name":"Query by Example","level":4,"score":0.0},{"id":"https://openalex.org/C164120249","wikidata":"https://www.wikidata.org/wiki/Q995982","display_name":"Web search query","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2021.3137536","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mm.2021.3137536","pdf_url":"https://ieeexplore.ieee.org/ielx7/40/9705173/09705183.pdf","source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/mm.2021.3137536","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mm.2021.3137536","pdf_url":"https://ieeexplore.ieee.org/ielx7/40/9705173/09705183.pdf","source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4210384431.pdf","grobid_xml":"https://content.openalex.org/works/W4210384431.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2084310805","https://openalex.org/W2493772236","https://openalex.org/W4293054943","https://openalex.org/W2491097902","https://openalex.org/W2993507867","https://openalex.org/W2104240303","https://openalex.org/W2361382102","https://openalex.org/W1991896026","https://openalex.org/W4312692645","https://openalex.org/W4210384431"],"abstract_inverted_index":{"The":[0],"articles":[1],"in":[2],"this":[3,33,54],"special":[4],"section":[5],"focuses":[6],"on":[7,61,67],"in-memory":[8],"computing.":[9],"Computer":[10],"designers":[11],"have":[12,73],"traditionally":[13],"separated":[14],"the":[15,42,58],"role":[16],"of":[17,76,102],"storage":[18],"and":[19,23,56,65,71],"compute":[20],"units.":[21],"Memories":[22],"caches":[24],"stored":[25],"data.":[26,68],"Processors\u2019":[27],"logic":[28],"units":[29,89],"computed":[30],"them.":[31],"Is":[32],"separation":[34],"necessary?":[35],"A":[36],"human":[37],"brain":[38],"does":[39],"not":[40],"separate":[41],"two":[43],"so":[44],"distinctly.":[45],"Why":[46],"should":[47],"a":[48,100],"processor?":[49],"In-/near-memory":[50,84],"computing":[51,66],"paradigm":[52],"blurs":[53],"distinction":[55],"imposes":[57],"dual":[59],"responsibility":[60],"memory":[62,88],"substrates:":[63],"storing":[64],"Modern":[69],"processors":[70],"accelerators":[72],"over":[74],"90%":[75],"their":[77],"aggregate":[78],"silicon":[79],"area":[80],"dedicated":[81],"to":[82],"memory.":[83],"processing":[85],"converts":[86],"these":[87],"into":[90],"powerful":[91],"allies":[92],"for":[93],"massively":[94],"parallel":[95],"computing,":[96],"which":[97],"can":[98],"accelerate":[99],"plethora":[101],"applications":[103],"including":[104],"neural":[105],"networks,":[106]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}