{"id":"https://openalex.org/W3130554079","doi":"https://doi.org/10.1109/mm.2021.3061394","title":"NVIDIA A100 Tensor Core GPU: Performance and Innovation","display_name":"NVIDIA A100 Tensor Core GPU: Performance and Innovation","publication_year":2021,"publication_date":"2021-02-23","ids":{"openalex":"https://openalex.org/W3130554079","doi":"https://doi.org/10.1109/mm.2021.3061394","mag":"3130554079"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2021.3061394","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2021.3061394","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082568014","display_name":"Jack Choquette","orcid":"https://orcid.org/0000-0002-3282-6777"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Jack Choquette","raw_affiliation_strings":["NVIDIA, Singapore"],"raw_orcid":"https://orcid.org/0000-0002-3282-6777","affiliations":[{"raw_affiliation_string":"NVIDIA, Singapore","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088675745","display_name":"Wishwesh Gandhi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wishwesh Gandhi","raw_affiliation_strings":["NVIDIA, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA, Singapore","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083397443","display_name":"Olivier Giroux","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Olivier Giroux","raw_affiliation_strings":["NVIDIA, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA, Singapore","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062017784","display_name":"Nick Stam","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nick Stam","raw_affiliation_strings":["NVIDIA, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA, Singapore","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004820034","display_name":"Ronny Krashinsky","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ronny Krashinsky","raw_affiliation_strings":["NVIDIA, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA, Singapore","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5082568014"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":56.1093,"has_fulltext":false,"cited_by_count":366,"citation_normalized_percentile":{"value":0.99969339,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":"41","issue":"2","first_page":"29","last_page":"35"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8732540607452393},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6325492858886719},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5672355890274048},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5522227883338928},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5326052904129028},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.49869632720947266},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.46602511405944824},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.45103156566619873},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.4218001961708069},{"id":"https://openalex.org/keywords/general-purpose-computing-on-graphics-processing-units","display_name":"General-purpose computing on graphics processing units","score":0.4147895872592926},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3431662917137146},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3251377046108246},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18192821741104126},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.1701039969921112}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8732540607452393},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6325492858886719},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5672355890274048},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5522227883338928},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5326052904129028},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.49869632720947266},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.46602511405944824},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.45103156566619873},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.4218001961708069},{"id":"https://openalex.org/C50630238","wikidata":"https://www.wikidata.org/wiki/Q971505","display_name":"General-purpose computing on graphics processing units","level":3,"score":0.4147895872592926},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3431662917137146},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3251377046108246},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18192821741104126},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.1701039969921112},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2021.3061394","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2021.3061394","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5899999737739563,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1970787534","https://openalex.org/W2798724095","https://openalex.org/W2979245724","https://openalex.org/W6769062451"],"related_works":["https://openalex.org/W1963859303","https://openalex.org/W2364044215","https://openalex.org/W2389600408","https://openalex.org/W240129890","https://openalex.org/W3048701459","https://openalex.org/W2149078538","https://openalex.org/W2080146221","https://openalex.org/W2370314112","https://openalex.org/W1912958759","https://openalex.org/W2792081825"],"abstract_inverted_index":{"NVIDIA":[0,52],"A100":[1],"Tensor":[2,36],"Core":[3],"GPU":[4],"is":[5],"NVIDIA's":[6],"latest":[7],"flagship":[8],"GPU.":[9],"It":[10],"has":[11],"been":[12],"designed":[13],"with":[14],"many":[15],"new":[16,38],"innovative":[17],"features":[18],"to":[19],"provide":[20],"performance":[21],"and":[22,27,42,50],"capabilities":[23],"for":[24],"HPC,":[25],"AI,":[26],"data":[28,40],"analytics":[29],"workloads.":[30],"Feature":[31],"enhancements":[32],"include":[33],"a":[34],"Third-Generation":[35],"Core,":[37],"asynchronous":[39],"movement":[41],"programming":[43],"model,":[44],"enhanced":[45],"L2":[46],"cache,":[47],"HBM2":[48],"DRAM,":[49],"third-generation":[51],"NVLink":[53],"I/O.":[54]},"counts_by_year":[{"year":2026,"cited_by_count":26},{"year":2025,"cited_by_count":100},{"year":2024,"cited_by_count":100},{"year":2023,"cited_by_count":68},{"year":2022,"cited_by_count":44},{"year":2021,"cited_by_count":26},{"year":2020,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-05-12T08:28:47.272897","created_date":"2025-10-10T00:00:00"}
