{"id":"https://openalex.org/W3031505651","doi":"https://doi.org/10.1109/mm.2020.2997610","title":"LastLayer: Toward Hardware and Software Continuous Integration","display_name":"LastLayer: Toward Hardware and Software Continuous Integration","publication_year":2020,"publication_date":"2020-05-25","ids":{"openalex":"https://openalex.org/W3031505651","doi":"https://doi.org/10.1109/mm.2020.2997610","mag":"3031505651"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2020.2997610","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2020.2997610","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075868532","display_name":"Luis Vega","orcid":"https://orcid.org/0000-0001-7185-9128"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Luis Vega","raw_affiliation_strings":["University of Washington"],"affiliations":[{"raw_affiliation_string":"University of Washington","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076140574","display_name":"Jared Roesch","orcid":null},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jared Roesch","raw_affiliation_strings":["University of Washington"],"affiliations":[{"raw_affiliation_string":"University of Washington","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000084643","display_name":"Joseph McMahan","orcid":null},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joseph McMahan","raw_affiliation_strings":["University of Washington"],"affiliations":[{"raw_affiliation_string":"University of Washington","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081914923","display_name":"Lu\u00eds Ceze","orcid":"https://orcid.org/0000-0002-1377-6217"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luis Ceze","raw_affiliation_strings":["University of Washington"],"affiliations":[{"raw_affiliation_string":"University of Washington","institution_ids":["https://openalex.org/I201448701"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5075868532"],"corresponding_institution_ids":["https://openalex.org/I201448701"],"apc_list":null,"apc_paid":null,"fwci":0.231,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.45455865,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"40","issue":"4","first_page":"103","last_page":"111"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8952585458755493},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6131768226623535},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5738216042518616},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5486196279525757},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5454550385475159},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.49416497349739075},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4576212167739868},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4452824294567108},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.38489094376564026},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3510303199291229},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.18452301621437073}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8952585458755493},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6131768226623535},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5738216042518616},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5486196279525757},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5454550385475159},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.49416497349739075},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4576212167739868},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4452824294567108},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.38489094376564026},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3510303199291229},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.18452301621437073},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2020.2997610","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2020.2997610","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/17","display_name":"Partnerships for the goals"}],"awards":[{"id":"https://openalex.org/G8924760687","display_name":null,"funder_award_id":"CCF-1518703","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1983394510","https://openalex.org/W2011645538","https://openalex.org/W2079751107","https://openalex.org/W2512813785","https://openalex.org/W2761973445","https://openalex.org/W2771610171","https://openalex.org/W2951749218","https://openalex.org/W4240172596","https://openalex.org/W6726186593"],"related_works":["https://openalex.org/W2357531057","https://openalex.org/W2136295006","https://openalex.org/W1761969858","https://openalex.org/W2165480138","https://openalex.org/W2107240870","https://openalex.org/W2107517480","https://openalex.org/W4231001357","https://openalex.org/W2131024837","https://openalex.org/W2393789539","https://openalex.org/W2132512458"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"LastLayer,":[3,104],"an":[4],"open-source":[5],"tool":[6],"that":[7,40,54],"enables":[8],"hardware":[9,77,88,112],"and":[10,14,66,90,121],"software":[11,83],"continuous":[12],"integration":[13,84,109],"simulation.":[15,78],"Compared":[16],"to":[17,60,100],"traditional":[18],"testing":[19,33],"approaches":[20],"based":[21],"on":[22],"the":[23,42,69,76],"register":[24],"transfer":[25],"level":[26],"abstraction,":[27],"LastLayer":[28,80],"provides":[29],"a":[30,50,111,122],"mechanism":[31],"for":[32,95],"Verilog":[34,116],"designs":[35],"with":[36],"any":[37,87],"programming":[38],"language":[39,93],"supports":[41,49],"C":[43,52],"foreign":[44],"function":[45],"interface.":[46],"Furthermore,":[47],"it":[48],"generic":[51],"interface":[53],"allows":[55],"external":[56],"programs":[57],"convenient":[58],"access":[59],"storage":[61,97],"resources":[62,98],"such":[63],"as":[64,71,73],"registers":[65],"memories":[67],"in":[68,115,126],"design":[70],"well":[72],"control":[74],"over":[75,118],"Moreover,":[79],"achieves":[81],"this":[82],"without":[85],"requiring":[86],"modification":[89],"automatically":[91],"generates":[92],"bindings":[94],"these":[96],"according":[99],"user":[101],"specification.":[102],"Using":[103],"we":[105],"evaluated":[106],"two":[107],"representative":[108],"examples:":[110],"adder":[113],"written":[114,125],"operating":[117],"NumPy":[119],"arrays,":[120],"ReLu":[123],"vector-accelerator":[124],"Chisel":[127],"processing":[128],"tensors":[129],"from":[130],"PyTorch.":[131]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}