{"id":"https://openalex.org/W3027559990","doi":"https://doi.org/10.1109/mm.2020.2995854","title":"OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs","display_name":"OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs","publication_year":2020,"publication_date":"2020-05-21","ids":{"openalex":"https://openalex.org/W3027559990","doi":"https://doi.org/10.1109/mm.2020.2995854","mag":"3027559990"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2020.2995854","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mm.2020.2995854","pdf_url":"https://ieeexplore.ieee.org/ielx7/40/9130972/09098028.pdf","source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://ieeexplore.ieee.org/ielx7/40/9130972/09098028.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103004961","display_name":"Xifan Tang","orcid":"https://orcid.org/0000-0003-2203-3981"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xifan Tang","raw_affiliation_strings":["University of Utah"],"affiliations":[{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055536889","display_name":"Edouard Giacomin","orcid":"https://orcid.org/0000-0002-5415-1870"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Edouard Giacomin","raw_affiliation_strings":["University of Utah"],"affiliations":[{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005320274","display_name":"Baudouin Chauviere","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baudouin Chauviere","raw_affiliation_strings":["University of Utah"],"affiliations":[{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046240202","display_name":"Aur\u00e9lien Alacchi","orcid":"https://orcid.org/0000-0002-4486-413X"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aurelien Alacchi","raw_affiliation_strings":["University of Utah"],"affiliations":[{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["University of Utah"],"affiliations":[{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5103004961"],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":2.4963,"has_fulltext":true,"cited_by_count":65,"citation_normalized_percentile":{"value":0.89622434,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":98,"max":100},"biblio":{"volume":"40","issue":"4","first_page":"41","last_page":"48"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8651511669158936},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8573359847068787},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.7303553819656372},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7228208184242249},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6382341384887695},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.603065550327301},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.5741441249847412},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5006814002990723},{"id":"https://openalex.org/keywords/agile-software-development","display_name":"Agile software development","score":0.4113909602165222},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.17475920915603638}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8651511669158936},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8573359847068787},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.7303553819656372},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7228208184242249},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6382341384887695},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.603065550327301},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.5741441249847412},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5006814002990723},{"id":"https://openalex.org/C14185376","wikidata":"https://www.wikidata.org/wiki/Q30232","display_name":"Agile software development","level":2,"score":0.4113909602165222},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.17475920915603638},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2020.2995854","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mm.2020.2995854","pdf_url":"https://ieeexplore.ieee.org/ielx7/40/9130972/09098028.pdf","source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/mm.2020.2995854","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mm.2020.2995854","pdf_url":"https://ieeexplore.ieee.org/ielx7/40/9130972/09098028.pdf","source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.6000000238418579,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G2475163961","display_name":null,"funder_award_id":"FA8650-18-2-7855.","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"},{"id":"https://openalex.org/G456446722","display_name":null,"funder_award_id":"FA8650-18-2-7855","funder_id":"https://openalex.org/F4320338294","funder_display_name":"Air Force Research Laboratory"},{"id":"https://openalex.org/G5649888554","display_name":null,"funder_award_id":"FA8650-18-2-7855","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"}],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320332815","display_name":"Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320338294","display_name":"Air Force Research Laboratory","ror":"https://ror.org/02e2egq70"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3027559990.pdf","grobid_xml":"https://content.openalex.org/works/W3027559990.grobid-xml"},"referenced_works_count":11,"referenced_works":["https://openalex.org/W2005602803","https://openalex.org/W2094756095","https://openalex.org/W2111427553","https://openalex.org/W2130276110","https://openalex.org/W2150022482","https://openalex.org/W2558383080","https://openalex.org/W2604877941","https://openalex.org/W2787754266","https://openalex.org/W2951713654","https://openalex.org/W2988212920","https://openalex.org/W3003845102"],"related_works":["https://openalex.org/W2365569181","https://openalex.org/W3202354107","https://openalex.org/W4286816096","https://openalex.org/W2924890221","https://openalex.org/W4306967480","https://openalex.org/W2165456233","https://openalex.org/W2348758434","https://openalex.org/W1975607764","https://openalex.org/W2005854230","https://openalex.org/W2163916557"],"abstract_inverted_index":{"Demanded":[0],"by":[1],"ever-evolving":[2],"data":[3],"processing":[4],"algorithms,":[5],"field-programmable":[6],"gate":[7],"arrays":[8],"(FPGAs)":[9],"have":[10],"become":[11],"essential":[12],"components":[13],"of":[14,67,135],"modern":[15],"computing":[16,24],"systems,":[17],"thanks":[18],"to":[19,74,80,102,115],"their":[20,76],"reconfigurable":[21],"and":[22,41,61,89,154],"distributed":[23],"capabilities.":[25],"However,":[26],"FPGAs":[27,121],"are":[28,140],"among":[29],"the":[30,64],"very":[31],"few":[32],"integrated":[33],"chips":[34],"that":[35,58,122],"still":[36],"require":[37],"long":[38],"development":[39,65],"cycles":[40],"high":[42],"human":[43],"efforts,":[44],"even":[45],"for":[46],"industrial":[47],"vendors.":[48],"In":[49],"this":[50],"article,":[51],"we":[52,128],"introduce":[53],"OpenFPGA,":[54,127],"an":[55],"open-source":[56],"framework":[57],"can":[59,95,124],"automate":[60],"significantly":[62],"accelerate":[63],"cycle":[66],"customizable":[68],"FPGA":[69,77,137],"architectures.":[70],"OpenFPGA":[71,123],"allows":[72],"users":[73],"customize":[75],"architectures":[78],"down":[79],"circuit-level":[81],"details":[82],"using":[83],"a":[84,99,143,148],"high-level":[85],"architecture":[86,145],"description":[87],"language":[88],"autogenerate":[90],"associated":[91],"Verilog":[92],"netlists":[93],"which":[94,139],"be":[96],"used":[97],"in":[98],"backend":[100],"flow":[101],"generate":[103],"production-ready":[104],"layouts.":[105],"A":[106],"generic":[107],"Verilog-to-Bitstream":[108],"generator":[109],"is":[110],"also":[111],"provided,":[112],"allowing":[113],"end-users":[114],"implement":[116],"practical":[117],"applications":[118],"on":[119,142],"any":[120],"support.":[125],"Using":[126],"demonstrate":[129],"less":[130],"than":[131],"24-h":[132],"layout":[133],"generation":[134],"two":[136],"fabrics,":[138],"based":[141],"Stratix-like":[144],"built":[146],"with":[147],"commercial":[149],"12-nm":[150],"standard":[151],"cell":[152],"library":[153],"40-nm":[155],"custom":[156],"cells,":[157],"respectively.":[158]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":20},{"year":2024,"cited_by_count":17},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":7}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}