{"id":"https://openalex.org/W2985830373","doi":"https://doi.org/10.1109/mm.2019.2942978","title":"Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration","display_name":"Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W2985830373","doi":"https://doi.org/10.1109/mm.2019.2942978","mag":"2985830373"},"language":"ca","primary_location":{"id":"doi:10.1109/mm.2019.2942978","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2019.2942978","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036105393","display_name":"Suman Datta","orcid":"https://orcid.org/0000-0001-6044-5173"},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Suman Datta","raw_affiliation_strings":["University of Notre Dame"],"raw_orcid":"https://orcid.org/0000-0001-6044-5173","affiliations":[{"raw_affiliation_string":"University of Notre Dame","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040063710","display_name":"Sourav Dutta","orcid":"https://orcid.org/0000-0001-5722-7909"},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sourav Dutta","raw_affiliation_strings":["University of Notre Dame"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Notre Dame","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051038074","display_name":"Benjamin Grisafe","orcid":"https://orcid.org/0000-0002-4271-3071"},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benjamin Grisafe","raw_affiliation_strings":["University of Notre Dame"],"raw_orcid":"https://orcid.org/0000-0002-4271-3071","affiliations":[{"raw_affiliation_string":"University of Notre Dame","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111484686","display_name":"Jeff Smith","orcid":null},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeff Smith","raw_affiliation_strings":["University of Notre Dame"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Notre Dame","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066731099","display_name":"Srivatsa Srinivasa","orcid":"https://orcid.org/0000-0002-3146-6642"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srivatsa Srinivasa","raw_affiliation_strings":["The Pennsylvania State University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Pennsylvania State University","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061840473","display_name":"Huacheng Ye","orcid":"https://orcid.org/0000-0003-3800-1335"},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Huacheng Ye","raw_affiliation_strings":["University of Notre Dame"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Notre Dame","institution_ids":["https://openalex.org/I107639228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.328,"has_fulltext":false,"cited_by_count":167,"citation_normalized_percentile":{"value":0.96319267,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":100},"biblio":{"volume":"39","issue":"6","first_page":"8","last_page":"15"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6693768501281738},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5394569039344788},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5314891338348389},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4995400905609131},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.4739791750907898},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.4678792357444763},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4261506497859955},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4142841100692749},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.33019840717315674},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16005733609199524},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12439361214637756}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6693768501281738},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5394569039344788},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5314891338348389},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4995400905609131},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.4739791750907898},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.4678792357444763},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4261506497859955},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4142841100692749},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.33019840717315674},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16005733609199524},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12439361214637756}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2019.2942978","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2019.2942978","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1745106164","https://openalex.org/W2000904597","https://openalex.org/W2097069052","https://openalex.org/W2124340473","https://openalex.org/W2128762553","https://openalex.org/W2132729131","https://openalex.org/W2146704626","https://openalex.org/W2168103591","https://openalex.org/W2731422849","https://openalex.org/W2784309942","https://openalex.org/W3203992401","https://openalex.org/W6656594533","https://openalex.org/W6674762609"],"related_works":["https://openalex.org/W3165307257","https://openalex.org/W2515312339","https://openalex.org/W2145098804","https://openalex.org/W4226211266","https://openalex.org/W2991151827","https://openalex.org/W2130440338","https://openalex.org/W1574518580","https://openalex.org/W2791832526","https://openalex.org/W2580900324","https://openalex.org/W2161229876"],"abstract_inverted_index":{"The":[0,65],"manufacturers":[1,70],"of":[2,9,29,50,98,105,118,128,136,151,161,175,190],"high-performance":[3,119],"logic":[4],"have":[5,41,57,71],"been":[6],"ardent":[7],"champions":[8],"Moore's":[10],"Law,":[11],"which":[12],"has":[13],"resulted":[14],"in":[15,18,108,133,170],"exponential":[16],"increase":[17],"aerial":[19],"transistor":[20],"density":[21],"to":[22,123,182],"100":[23],"million":[24],"transistors":[25,157,181],"per":[26],"square":[27],"millimeter":[28],"silicon":[30,79],"real":[31],"estate.":[32],"However,":[33],"it":[34],"is":[35],"the":[36,43,48,53,59,62,78,83,89,125,159,171],"memory":[37,69,92],"chip":[38],"makers":[39],"who":[40],"taken":[42],"first":[44],"step":[45],"toward":[46],"escaping":[47],"confines":[49],"scaling":[51],"within":[52],"horizontal":[54],"plane":[55,80],"and":[56,85,140,173],"embraced":[58],"vertical":[60],"or":[61],"third":[63],"dimension.":[64],"dynamic":[66],"random":[67],"access":[68,84],"adopted":[72],"stacked":[73],"capacitors":[74],"that":[75,81,145],"tower":[76],"above":[77],"hosts":[82],"peripheral":[86],"transistors,":[87],"whereas":[88],"nand":[90],"flash":[91,101],"technologists":[93],"can":[94,146],"stack":[95],"128":[96],"layers":[97],"charge":[99],"trap":[100],"cells":[102],"on":[103],"top":[104],"each":[106],"other":[107],"a":[109,188],"monolithic":[110,114],"fashion.":[111],"To":[112],"enable":[113,183],"three-dimensional":[115],"(M3D)":[116],"integration":[117,186],"logic,":[120],"one":[121],"needs":[122],"solve":[124],"fundamental":[126],"challenge":[127],"low":[129],"temperature":[130],"(<400":[131],"\u00b0C)":[132],"situ":[134],"synthesis":[135],"high":[137],"mobility":[138],"n-type":[139],"p-type":[141],"semiconductor":[142,176],"thin":[143],"films":[144],"be":[147],"utilized":[148],"for":[149,178,187],"fabrication":[150],"back-end-of-line":[152],"(BEOL)":[153],"compatible":[154,180],"complementary":[155],"MOS":[156],"under":[158],"constraint":[160],"limited":[162],"thermal":[163],"budget.":[164],"This":[165],"article":[166],"discusses":[167],"recent":[168],"progress":[169],"selection":[172],"optimization":[174],"materials":[177],"BEOL":[179],"sequential":[184],"M3D":[185],"range":[189],"applications.":[191]},"counts_by_year":[{"year":2026,"cited_by_count":22},{"year":2025,"cited_by_count":40},{"year":2024,"cited_by_count":33},{"year":2023,"cited_by_count":28},{"year":2022,"cited_by_count":18},{"year":2021,"cited_by_count":19},{"year":2020,"cited_by_count":7}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
