{"id":"https://openalex.org/W2761686942","doi":"https://doi.org/10.1109/mm.2017.3711654","title":"Offloading Collective Operations to Programmable Logic","display_name":"Offloading Collective Operations to Programmable Logic","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2761686942","doi":"https://doi.org/10.1109/mm.2017.3711654","mag":"2761686942"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2017.3711654","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2017.3711654","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026031178","display_name":"Omer Arap","orcid":null},"institutions":[{"id":"https://openalex.org/I592451","display_name":"Indiana University","ror":"https://ror.org/01kg8sb98","country_code":"US","type":"education","lineage":["https://openalex.org/I592451"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Omer Arap","raw_affiliation_strings":["Indiana University"],"affiliations":[{"raw_affiliation_string":"Indiana University","institution_ids":["https://openalex.org/I592451"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076356696","display_name":"Lucas R. B. Brasilino","orcid":null},"institutions":[{"id":"https://openalex.org/I592451","display_name":"Indiana University","ror":"https://ror.org/01kg8sb98","country_code":"US","type":"education","lineage":["https://openalex.org/I592451"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lucas R.B. Brasilino","raw_affiliation_strings":["Indiana University"],"affiliations":[{"raw_affiliation_string":"Indiana University","institution_ids":["https://openalex.org/I592451"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066848682","display_name":"Ezra Kissel","orcid":"https://orcid.org/0000-0003-3972-9651"},"institutions":[{"id":"https://openalex.org/I592451","display_name":"Indiana University","ror":"https://ror.org/01kg8sb98","country_code":"US","type":"education","lineage":["https://openalex.org/I592451"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ezra Kissel","raw_affiliation_strings":["Indiana University"],"affiliations":[{"raw_affiliation_string":"Indiana University","institution_ids":["https://openalex.org/I592451"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047577934","display_name":"Alexander Shroyer","orcid":"https://orcid.org/0000-0002-6291-3994"},"institutions":[{"id":"https://openalex.org/I592451","display_name":"Indiana University","ror":"https://ror.org/01kg8sb98","country_code":"US","type":"education","lineage":["https://openalex.org/I592451"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexander Shroyer","raw_affiliation_strings":["Indiana University"],"affiliations":[{"raw_affiliation_string":"Indiana University","institution_ids":["https://openalex.org/I592451"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044461835","display_name":"Martin Swany","orcid":"https://orcid.org/0000-0001-8028-1161"},"institutions":[{"id":"https://openalex.org/I592451","display_name":"Indiana University","ror":"https://ror.org/01kg8sb98","country_code":"US","type":"education","lineage":["https://openalex.org/I592451"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Martin Swany","raw_affiliation_strings":["Intelligent Systems Engineering Department, Indiana University"],"affiliations":[{"raw_affiliation_string":"Intelligent Systems Engineering Department, Indiana University","institution_ids":["https://openalex.org/I592451"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5026031178"],"corresponding_institution_ids":["https://openalex.org/I592451"],"apc_list":null,"apc_paid":null,"fwci":0.5932,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.68272906,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"37","issue":"5","first_page":"52","last_page":"60"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12784","display_name":"Modular Robots and Swarm Intelligence","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2210","display_name":"Mechanical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12784","display_name":"Modular Robots and Swarm Intelligence","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2210","display_name":"Mechanical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8778241872787476},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.6586188673973083},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6215682625770569},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6131460666656494},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5568601489067078},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5333656668663025},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5256812572479248},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.5237200856208801},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.46624651551246643},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46487167477607727},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.452757328748703},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.436975359916687},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.4125162959098816},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3921990692615509},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.38864046335220337},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24826160073280334},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.21700921654701233},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.17871025204658508},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15396887063980103},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.12744590640068054}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8778241872787476},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.6586188673973083},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6215682625770569},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6131460666656494},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5568601489067078},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5333656668663025},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5256812572479248},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.5237200856208801},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.46624651551246643},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46487167477607727},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.452757328748703},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.436975359916687},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.4125162959098816},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3921990692615509},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.38864046335220337},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24826160073280334},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.21700921654701233},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.17871025204658508},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15396887063980103},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.12744590640068054},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2017.3711654","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2017.3711654","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W123010799","https://openalex.org/W1644418078","https://openalex.org/W1962396625","https://openalex.org/W2040882418","https://openalex.org/W2062764889","https://openalex.org/W2097982440","https://openalex.org/W2099020156","https://openalex.org/W2105800835","https://openalex.org/W2115020004","https://openalex.org/W2123859357","https://openalex.org/W2534577245"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3117015220","https://openalex.org/W3013792460","https://openalex.org/W2466591189","https://openalex.org/W3022525969","https://openalex.org/W2764789987","https://openalex.org/W2014165129","https://openalex.org/W1904803855","https://openalex.org/W4389045693","https://openalex.org/W2376859467"],"abstract_inverted_index":{"The":[0,53,73],"authors":[1,102],"describe":[2],"their":[3,117],"architecture":[4],"and":[5,28,89,127,142],"implementation":[6,29],"for":[7,66,109],"offloading":[8,107],"collective":[9,106],"operations":[10,19],"to":[11,45,70,93],"programmable":[12,54,83],"logic":[13,55,69,84],"in":[14,23,78,85,111],"the":[15,32,46,86,101,120,134],"communication":[16,87],"substrate.":[17],"Collective":[18],"are":[20,43,137],"widely":[21],"used":[22,92],"parallel":[24],"processing.":[25],"Their":[26],"design":[27],"strategies":[30],"affect":[31],"performance":[33],"of":[34],"many":[35],"high-performance":[36],"computing":[37],"applications":[38,112],"that":[39],"utilize":[40],"them.":[41],"Collectives":[42],"central":[44],"message":[47],"passing":[48],"interface":[49,131],"(MPI)":[50],"programming":[51],"model.":[52],"provided":[56],"by":[57],"field-programmable":[58],"gate":[59],"arrays":[60],"(FPGAs)":[61],"is":[62,76,82],"a":[63,104,125,143],"powerful":[64],"option":[65],"creating":[67],"task-specific":[68],"aid":[71],"applications.":[72],"authors'":[74],"approach":[75,118],"applicable":[77],"scenarios":[79],"where":[80],"there":[81],"pipeline":[88],"can":[90],"be":[91],"accelerate":[94],"various":[95],"network-based":[96],"operations.":[97],"In":[98],"this":[99],"article,":[100],"present":[103],"general":[105],"framework":[108],"use":[110],"using":[113,147],"MPI.":[114,148],"They":[115],"evaluate":[116],"on":[119,124],"Xilinx":[121],"Zynq":[122],"system":[123],"chip":[126],"an":[128],"FPGA-based":[129],"network":[130],"card":[132],"called":[133],"NetFPGA.":[135],"Results":[136],"presented":[138],"both":[139],"from":[140],"microbenchmarks":[141],"benchmark":[144],"scientific":[145],"application":[146]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}