{"id":"https://openalex.org/W2338919664","doi":"https://doi.org/10.1109/mm.2016.18","title":"A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform","display_name":"A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform","publication_year":2016,"publication_date":"2016-03-01","ids":{"openalex":"https://openalex.org/W2338919664","doi":"https://doi.org/10.1109/mm.2016.18","mag":"2338919664"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2016.18","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2016.18","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112417677","display_name":"Sagheer Ahmad","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sagheer Ahmad","raw_affiliation_strings":["Xilinx"],"affiliations":[{"raw_affiliation_string":"Xilinx","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112761076","display_name":"Vamsi Boppana","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vamsi Boppana","raw_affiliation_strings":["Xilinx"],"affiliations":[{"raw_affiliation_string":"Xilinx","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091859340","display_name":"Ilya Ganusov","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ilya Ganusov","raw_affiliation_strings":["Xilinx"],"affiliations":[{"raw_affiliation_string":"Xilinx","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027587937","display_name":"Vinod Kathail","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vinod Kathail","raw_affiliation_strings":["Xilinx"],"affiliations":[{"raw_affiliation_string":"Xilinx","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032096296","display_name":"Vidya Rajagopalan","orcid":"https://orcid.org/0009-0003-6569-0604"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vidya Rajagopalan","raw_affiliation_strings":["Xilinx"],"affiliations":[{"raw_affiliation_string":"Xilinx","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030738948","display_name":"Ralph Wittig","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ralph Wittig","raw_affiliation_strings":["Xilinx"],"affiliations":[{"raw_affiliation_string":"Xilinx","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5112417677"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":4.73,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.95034794,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"36","issue":"2","first_page":"48","last_page":"62"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.9250690340995789},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8325945138931274},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.726338803768158},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6891534328460693},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6337680220603943},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5866798758506775},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5810497999191284},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47467660903930664},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4557076096534729},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4491420388221741},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.41442641615867615},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2771412134170532},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16957193613052368}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.9250690340995789},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8325945138931274},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.726338803768158},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6891534328460693},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6337680220603943},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5866798758506775},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5810497999191284},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47467660903930664},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4557076096534729},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4491420388221741},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.41442641615867615},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2771412134170532},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16957193613052368}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2016.18","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2016.18","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320308668","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2171768221","https://openalex.org/W2471791811","https://openalex.org/W6720585214"],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W2466591189","https://openalex.org/W2154814801","https://openalex.org/W2376859467","https://openalex.org/W1972395546","https://openalex.org/W2038293309","https://openalex.org/W2017736121","https://openalex.org/W3163714531","https://openalex.org/W4309935840","https://openalex.org/W2764789987"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"the":[3,14,19,31,35,38,47,51,60,71,75,86,106],"Zynq":[4],"UltraScale+":[5],"MPSoC":[6,22],"(multiprocessor":[7],"system":[8],"on":[9,13],"chip),":[10],"which":[11],"builds":[12],"Zynq-7000":[15],"family.":[16],"Compared":[17],"to":[18,101],"first-generation":[20],"Zynq,":[21],"increases":[23],"performance":[24],"and":[25,37,65,96],"power":[26],"efficiency":[27],"while":[28],"significantly":[29],"improving":[30],"integration":[32],"level":[33],"between":[34],"SoC":[36,108],"field-programmable":[39],"gate":[40],"array":[41],"(FPGA).":[42],"It":[43],"also":[44],"further":[45],"raises":[46],"programming":[48],"abstraction":[49],"with":[50,89],"introduction":[52],"of":[53,105],"a":[54,90,97,110],"new":[55,80],"heterogeneous":[56,107],"system-wide":[57,63],"compiler.":[58],"At":[59],"hardware":[61],"level,":[62],"coherency":[64],"shared":[66],"virtual":[67],"memory":[68],"bridge":[69],"across":[70],"processor":[72],"subsystem":[73],"into":[74],"programmable":[76],"logic":[77],"array.":[78],"The":[79],"SDSoC":[81],"(software-designed":[82],"SoC)":[83],"environment":[84],"combines":[85],"ARM":[87],"compiler":[88,95,100],"high-level":[91],"synthesis":[92],"technology-based":[93],"FPGA":[94],"full-system":[98],"optimizing":[99],"target":[102],"all":[103],"elements":[104],"from":[109],"common":[111],"program":[112],"source.":[113]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}