{"id":"https://openalex.org/W2148954445","doi":"https://doi.org/10.1109/mm.2004.1289290","title":"IBM power5 chip: a dual-core multithreaded processor","display_name":"IBM power5 chip: a dual-core multithreaded processor","publication_year":2004,"publication_date":"2004-03-01","ids":{"openalex":"https://openalex.org/W2148954445","doi":"https://doi.org/10.1109/mm.2004.1289290","mag":"2148954445"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2004.1289290","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2004.1289290","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109981773","display_name":"R. Kalla","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"R. Kalla","raw_affiliation_strings":["IBM, USA"],"affiliations":[{"raw_affiliation_string":"IBM, USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002320585","display_name":"Balaram Sinharoy","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Sinharoy","raw_affiliation_strings":["IBM, USA"],"affiliations":[{"raw_affiliation_string":"IBM, USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078842998","display_name":"Joel M. Tendler","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.M. Tendler","raw_affiliation_strings":["IBM, USA"],"affiliations":[{"raw_affiliation_string":"IBM, USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5109981773"],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":44.1034,"has_fulltext":false,"cited_by_count":366,"citation_normalized_percentile":{"value":1.0,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":"24","issue":"2","first_page":"40","last_page":"47"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8614067435264587},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6177113056182861},{"id":"https://openalex.org/keywords/ibm","display_name":"IBM","score":0.5464906692504883},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5350645184516907},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.48676538467407227},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.46302902698516846},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.46297332644462585},{"id":"https://openalex.org/keywords/simultaneous-multithreading","display_name":"Simultaneous multithreading","score":0.43444162607192993},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4327578544616699},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.42640602588653564},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.42469322681427},{"id":"https://openalex.org/keywords/directory","display_name":"Directory","score":0.419874906539917}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8614067435264587},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6177113056182861},{"id":"https://openalex.org/C70388272","wikidata":"https://www.wikidata.org/wiki/Q5968558","display_name":"IBM","level":2,"score":0.5464906692504883},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5350645184516907},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.48676538467407227},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.46302902698516846},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.46297332644462585},{"id":"https://openalex.org/C85717602","wikidata":"https://www.wikidata.org/wiki/Q82178","display_name":"Simultaneous multithreading","level":4,"score":0.43444162607192993},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4327578544616699},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.42640602588653564},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.42469322681427},{"id":"https://openalex.org/C2777683733","wikidata":"https://www.wikidata.org/wiki/Q201456","display_name":"Directory","level":2,"score":0.419874906539917},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2004.1289290","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2004.1289290","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1554040407","https://openalex.org/W1995140396","https://openalex.org/W2081040934","https://openalex.org/W2120230074","https://openalex.org/W2122563027","https://openalex.org/W2622728018","https://openalex.org/W2916411819","https://openalex.org/W3142147837","https://openalex.org/W6678438195"],"related_works":["https://openalex.org/W2118532220","https://openalex.org/W4240807263","https://openalex.org/W2115561485","https://openalex.org/W1985089255","https://openalex.org/W2153202644","https://openalex.org/W2380961080","https://openalex.org/W2010970156","https://openalex.org/W4235861380","https://openalex.org/W2106625514","https://openalex.org/W1867214769"],"abstract_inverted_index":{"IBM":[0],"introduced":[1],"Power4-based":[2],"systems":[3,83],"in":[4,60,68],"2001.":[5],"The":[6,43,54],"Power4":[7,37,82],"design":[8],"integrates":[9],"two":[10],"processor":[11],"cores":[12],"on":[13],"a":[14,17,21,41],"single":[15],"chip,":[16],"shared":[18],"second-level":[19],"cache,":[20,27],"directory":[22],"for":[23],"an":[24],"off-chip":[25],"third-level":[26],"and":[28,77,91,108,117,122],"the":[29,51,57,70,127],"necessary":[30],"circuitry":[31],"to":[32,35,39,73,84,97,131],"connect":[33],"it":[34],"other":[36,109],"chips":[38],"form":[40],"system.":[42],"dual-processor":[44],"chip":[45,52,59,121],"provides":[46],"natural":[47],"thread-level":[48],"parallelism":[49],"at":[50,119],"level.":[53],"Power5":[55,71],"is":[56],"next-generation":[58],"this":[61],"line.":[62],"One":[63],"of":[64,112],"our":[65],"key":[66],"goals":[67],"designing":[69],"was":[72],"maintain":[74],"both":[75,120],"binary":[76],"structural":[78],"compatibility":[79],"with":[80],"existing":[81],"ensure":[85],"that":[86,101],"binaries":[87],"continue":[88],"executing":[89],"properly":[90],"all":[92],"application":[93],"optimizations":[94],"carry":[95],"forward":[96],"newer":[98],"systems.":[99],"With":[100],"base":[102],"requirement,":[103],"we":[104,129],"specified":[105],"increased":[106],"performance":[107],"functional":[110],"enhancements":[111],"server":[113],"virtualization,":[114],"reliability,":[115],"availability,":[116],"serviceability":[118],"system":[123],"levels.":[124],"We":[125],"describe":[126],"approach":[128],"used":[130],"improve":[132],"chip-level":[133],"performance.":[134]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":15}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}