{"id":"https://openalex.org/W2072163596","doi":"https://doi.org/10.1109/mm.2002.1044299","title":"A scalable high-performance computing solution for networks on chips","display_name":"A scalable high-performance computing solution for networks on chips","publication_year":2002,"publication_date":"2002-09-01","ids":{"openalex":"https://openalex.org/W2072163596","doi":"https://doi.org/10.1109/mm.2002.1044299","mag":"2072163596"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2002.1044299","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2002.1044299","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091679053","display_name":"Martti Forsell","orcid":"https://orcid.org/0000-0003-4865-8058"},"institutions":[{"id":"https://openalex.org/I87653560","display_name":"VTT Technical Research Centre of Finland","ror":"https://ror.org/04b181w54","country_code":"FI","type":"nonprofit","lineage":["https://openalex.org/I4210089493","https://openalex.org/I87653560"]}],"countries":["FI"],"is_corresponding":true,"raw_author_name":"M. Forsell","raw_affiliation_strings":["VTT Electronics, Finland","BA1511 Efficient computing and communications"],"affiliations":[{"raw_affiliation_string":"VTT Electronics, Finland","institution_ids":["https://openalex.org/I87653560"]},{"raw_affiliation_string":"BA1511 Efficient computing and communications","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5091679053"],"corresponding_institution_ids":["https://openalex.org/I87653560"],"apc_list":null,"apc_paid":null,"fwci":6.51133895,"has_fulltext":false,"cited_by_count":119,"citation_normalized_percentile":{"value":0.96921542,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"22","issue":"5","first_page":"46","last_page":"55"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9914000034332275,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8934518098831177},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6962913870811462},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6715761423110962},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6082616448402405},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5365882515907288},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4815671443939209},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.44515568017959595},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.41832441091537476},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4013841450214386},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3952281177043915},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2190530002117157},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14419639110565186}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8934518098831177},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6962913870811462},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6715761423110962},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6082616448402405},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5365882515907288},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4815671443939209},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.44515568017959595},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.41832441091537476},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4013841450214386},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3952281177043915},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2190530002117157},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14419639110565186},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2002.1044299","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2002.1044299","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1481186594","https://openalex.org/W1490063922","https://openalex.org/W2004618348","https://openalex.org/W2011403724","https://openalex.org/W2077229436","https://openalex.org/W2119677480","https://openalex.org/W2160642395","https://openalex.org/W4245203543","https://openalex.org/W6629407263"],"related_works":["https://openalex.org/W2889526943","https://openalex.org/W2019683599","https://openalex.org/W121182129","https://openalex.org/W2360310172","https://openalex.org/W2517841089","https://openalex.org/W4863605","https://openalex.org/W4285287318","https://openalex.org/W2784141701","https://openalex.org/W2138821532","https://openalex.org/W1978899622"],"abstract_inverted_index":{"The":[0],"Eclipse":[1],"network-on-a-chip":[2],"architecture":[3],"uses":[4],"a":[5,18],"sophisticated":[6],"parallel":[7],"programming":[8],"model,":[9],"realized":[10],"through":[11],"multithreaded":[12],"processors,":[13],"interleaved":[14],"memory":[15],"modules,":[16],"and":[17],"high-capacity":[19],"interconnection":[20],"network":[21],"to":[22],"support":[23],"system-on-a-chip":[24],"designs.":[25]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":8},{"year":2012,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
