{"id":"https://openalex.org/W2031273683","doi":"https://doi.org/10.1109/mm.2002.1044296","title":"Chain: a delay-insensitive chip area interconnect","display_name":"Chain: a delay-insensitive chip area interconnect","publication_year":2002,"publication_date":"2002-09-01","ids":{"openalex":"https://openalex.org/W2031273683","doi":"https://doi.org/10.1109/mm.2002.1044296","mag":"2031273683"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2002.1044296","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2002.1044296","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027781767","display_name":"John Bainbridge","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"J. Bainbridge","raw_affiliation_strings":["University of Manchester, Institute of Science and Technology, UK","Dept. of Comput. Sci., Manchester Univ., UK#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Manchester, Institute of Science and Technology, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Manchester Univ., UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083177159","display_name":"Steve Furber","orcid":"https://orcid.org/0000-0002-6524-3367"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"S. Furber","raw_affiliation_strings":["University of Manchester, Institute of Science and Technology, UK","Dept. of Comput. Sci., Manchester Univ., UK#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Manchester, Institute of Science and Technology, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Manchester Univ., UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5027781767"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":6.6977,"has_fulltext":false,"cited_by_count":225,"citation_normalized_percentile":{"value":0.972555,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"22","issue":"5","first_page":"16","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7996079921722412},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6017404794692993},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5790666341781616},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5002965927124023},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4654914140701294},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.434373676776886},{"id":"https://openalex.org/keywords/chain","display_name":"Chain (unit)","score":0.4126884937286377},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40652579069137573},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.340513676404953},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32788074016571045},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.26686355471611023}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7996079921722412},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6017404794692993},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5790666341781616},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5002965927124023},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4654914140701294},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.434373676776886},{"id":"https://openalex.org/C199185054","wikidata":"https://www.wikidata.org/wiki/Q552299","display_name":"Chain (unit)","level":2,"score":0.4126884937286377},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40652579069137573},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.340513676404953},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32788074016571045},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.26686355471611023},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/mm.2002.1044296","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2002.1044296","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/79ea35c7-f240-42f4-a2d8-23d9b815cd28","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/79ea35c7-f240-42f4-a2d8-23d9b815cd28","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Bainbridge, J & Furber, S 2002, 'Chain: A delay-insensitive chip area interconnect', IEEE Micro, vol. 22, no. 5, pp. 16-23. https://doi.org/10.1109/MM.2002.1044296","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:pure.atira.dk:publications/79ea35c7-f240-42f4-a2d8-23d9b815cd28","is_oa":false,"landing_page_url":"http://dblp.uni-trier.de/rec/bibtex/journals/micro/BainbridgeF02","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Bainbridge, J & Furber, S 2002, 'Chain: A delay-insensitive chip area interconnect', IEEE Micro, vol. 22, no. 5, pp. 16-23. https://doi.org/10.1109/MM.2002.1044296","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1546435617","https://openalex.org/W1556480701","https://openalex.org/W1999082644","https://openalex.org/W2122623069","https://openalex.org/W2123184444","https://openalex.org/W2132339613","https://openalex.org/W2138356887","https://openalex.org/W2146587443","https://openalex.org/W2153186550","https://openalex.org/W2157617940","https://openalex.org/W2161849579","https://openalex.org/W2911717499","https://openalex.org/W4231905827","https://openalex.org/W6805453576"],"related_works":["https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2144460576","https://openalex.org/W2018755015","https://openalex.org/W2098218272","https://openalex.org/W4244547561","https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2115579119","https://openalex.org/W2136854845"],"abstract_inverted_index":{"The":[0,15],"increasing":[1],"complexity":[2],"of":[3],"system-on-a-chip":[4],"designs":[5],"exposes":[6],"the":[7,11],"limits":[8],"imposed":[9],"by":[10],"standard":[12],"synchronous":[13],"bus.":[14],"authors":[16],"propose":[17],"a":[18,22],"mixed":[19],"system":[20],"as":[21],"solution.":[23]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":8},{"year":2012,"cited_by_count":10}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}