{"id":"https://openalex.org/W4415003297","doi":"https://doi.org/10.1109/mlcad65511.2025.11189110","title":"ML-Inspired Logic Synthesis: Improving Multiplier Circuits","display_name":"ML-Inspired Logic Synthesis: Improving Multiplier Circuits","publication_year":2025,"publication_date":"2025-09-08","ids":{"openalex":"https://openalex.org/W4415003297","doi":"https://doi.org/10.1109/mlcad65511.2025.11189110"},"language":"en","primary_location":{"id":"doi:10.1109/mlcad65511.2025.11189110","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mlcad65511.2025.11189110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 ACM/IEEE 7th Symposium on Machine Learning for CAD (MLCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079108909","display_name":"Yukio Miyasaka","orcid":"https://orcid.org/0000-0002-7960-9913"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yukio Miyasaka","raw_affiliation_strings":["University of California, Berkeley,Berkeley,California,USA"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley,Berkeley,California,USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028824039","display_name":"Walter Lau Neto","orcid":"https://orcid.org/0000-0002-9349-4964"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Walter Lau Neto","raw_affiliation_strings":["Synopsys Inc.,Sunnyvale,California,USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc.,Sunnyvale,California,USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033842260","display_name":"Eleonora Testa","orcid":"https://orcid.org/0000-0003-1114-8476"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eleonora Testa","raw_affiliation_strings":["Synopsys Inc.,Sunnyvale,California,USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc.,Sunnyvale,California,USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018309919","display_name":"Anantharaju Prasad","orcid":"https://orcid.org/0000-0002-7245-0110"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anika Prasad","raw_affiliation_strings":["Synopsys Inc.,Sunnyvale,California,USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc.,Sunnyvale,California,USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5119924973","display_name":"Michael Shuster","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Shuster","raw_affiliation_strings":["Synopsys Inc.,Sunnyvale,California,USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc.,Sunnyvale,California,USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033840690","display_name":"R. Zimmermann","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Reto Zimmermann","raw_affiliation_strings":["Synopsys Inc.,Sunnyvale,California,USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc.,Sunnyvale,California,USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006756374","display_name":"Patrick Vuillod","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patrick Vuillod","raw_affiliation_strings":["Synopsys Inc.,Sunnyvale,California,USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc.,Sunnyvale,California,USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["University of California, Berkeley,Berkeley,California,USA"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley,Berkeley,California,USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044520704","display_name":"John Wawrzynek","orcid":"https://orcid.org/0009-0003-1466-4553"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Wawrzynek","raw_affiliation_strings":["University of California, Berkeley,Berkeley,California,USA"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley,Berkeley,California,USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023405941","display_name":"Luca Amar\u00f9","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luca Amar\u00f9","raw_affiliation_strings":["Synopsys Inc.,Sunnyvale,California,USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc.,Sunnyvale,California,USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5079108909"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.32593222,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9682000279426575,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9682000279426575,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9549000263214111,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9455999732017517,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.647599995136261},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6212999820709229},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6004999876022339},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5891000032424927},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.557200014591217},{"id":"https://openalex.org/keywords/diode\u2013transistor-logic","display_name":"Diode\u2013transistor logic","score":0.4397999942302704},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.42989999055862427},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.42399999499320984}],"concepts":[{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.647599995136261},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6263999938964844},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6212999820709229},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6004999876022339},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5891000032424927},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.557200014591217},{"id":"https://openalex.org/C118759142","wikidata":"https://www.wikidata.org/wiki/Q173475","display_name":"Diode\u2013transistor logic","level":5,"score":0.4397999942302704},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.42989999055862427},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.42399999499320984},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41339999437332153},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36390000581741333},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.36169999837875366},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3249000012874603},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.31060001254081726},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3082999885082245},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.30649998784065247},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3034999966621399},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.2727000117301941},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.26809999346733093},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.2676999866962433},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2590999901294708},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25780001282691956},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.2556999921798706}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mlcad65511.2025.11189110","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mlcad65511.2025.11189110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 ACM/IEEE 7th Symposium on Machine Learning for CAD (MLCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2100465945","https://openalex.org/W2809037211","https://openalex.org/W2889669826","https://openalex.org/W2949676527","https://openalex.org/W3109579920","https://openalex.org/W3127733006","https://openalex.org/W3214138519","https://openalex.org/W4254067345","https://openalex.org/W4256548512","https://openalex.org/W4293023818","https://openalex.org/W4312939266","https://openalex.org/W4388017305","https://openalex.org/W4390553432","https://openalex.org/W4394998532","https://openalex.org/W4402570972"],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"ML-inspired":[4],"logic":[5,10,15,55,125],"synthesis":[6,91,126],"framework":[7,33,89],"to":[8,17,50,90,109,129],"synthesize":[9],"circuits":[11,56],"from":[12],"specification,":[13],"unlocking":[14],"optimization":[16],"reach":[18],"new,":[19],"unexplored,":[20],"solutions":[21],"in":[22,73,119,143],"the":[23,31,60,71,75,87,103,114,120],"design":[24],"space.":[25],"Based":[26],"on":[27,140],"a":[28,37,40,68,123],"given":[29],"template,":[30],"proposed":[32,88],"creates":[34],"and":[35,132,138],"trains":[36],"model":[38,76],"using":[39],"novel":[41],"backpropagation":[42],"method,":[43],"don\u2019t-care-based":[44],"backpropagation,":[45],"which":[46,74],"makes":[47],"it":[48],"possible":[49],"learn":[51],"non-differentiable":[52],"attributes":[53],"of":[54,92,122],"efficiently.":[57],"We":[58],"ensure":[59],"resulting":[61,97],"circuit":[62],"is":[63,77],"functionally":[64],"correct":[65],"by":[66],"adding":[67],"patch":[69],"for":[70],"cases":[72],"not":[78],"100%":[79],"accurate.":[80],"To":[81],"demonstrate":[82],"its":[83],"effectiveness,":[84],"we":[85],"apply":[86],"new":[93],"multiplier":[94],"circuits.":[95],"The":[96],"multipliers":[98,116],"are":[99],"significantly":[100],"smaller":[101],"than":[102],"best":[104],"known":[105],"implementations,":[106],"with":[107],"up":[108],"32.8%":[110],"area":[111,131],"reduction.":[112],"Finally,":[113],"generated":[115],"were":[117],"integrated":[118],"core":[121],"state-of-the-art":[124],"tool,":[127],"leading":[128],"1.98%":[130],"0.54%":[133],"WNS":[134],"reductions,":[135],"post":[136],"place":[137],"route,":[139],"designs":[141],"specialized":[142],"performing":[144],"AI":[145],"tasks.":[146]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-10-10T00:00:00"}