{"id":"https://openalex.org/W4388040391","doi":"https://doi.org/10.1109/mlcad58807.2023.10299859","title":"Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations","display_name":"Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations","publication_year":2023,"publication_date":"2023-09-10","ids":{"openalex":"https://openalex.org/W4388040391","doi":"https://doi.org/10.1109/mlcad58807.2023.10299859"},"language":"en","primary_location":{"id":"doi:10.1109/mlcad58807.2023.10299859","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mlcad58807.2023.10299859","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076455352","display_name":"Daniela S\u00e1nchez Lopera","orcid":"https://orcid.org/0000-0001-8750-7696"},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]},{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Daniela S\u00e1nchez Lopera","raw_affiliation_strings":["Infineon Technologies AG and Technical University of Munich,Germany","Infineon Technologies AG and Technical University of Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG and Technical University of Munich,Germany","institution_ids":["https://openalex.org/I137594350","https://openalex.org/I62916508"]},{"raw_affiliation_string":"Infineon Technologies AG and Technical University of Munich, Germany","institution_ids":["https://openalex.org/I137594350","https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ishwor Subedi","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]},{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ishwor Subedi","raw_affiliation_strings":["Infineon Technologies AG and Technical University of Munich,Germany","Infineon Technologies AG and Technical University of Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG and Technical University of Munich,Germany","institution_ids":["https://openalex.org/I137594350","https://openalex.org/I62916508"]},{"raw_affiliation_string":"Infineon Technologies AG and Technical University of Munich, Germany","institution_ids":["https://openalex.org/I137594350","https://openalex.org/I62916508"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046956677","display_name":"Wolfgang Ecker","orcid":"https://orcid.org/0000-0002-9362-8096"},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]},{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Ecker","raw_affiliation_strings":["Infineon Technologies AG and Technical University of Munich,Germany","Infineon Technologies AG and Technical University of Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG and Technical University of Munich,Germany","institution_ids":["https://openalex.org/I137594350","https://openalex.org/I62916508"]},{"raw_affiliation_string":"Infineon Technologies AG and Technical University of Munich, Germany","institution_ids":["https://openalex.org/I137594350","https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5076455352"],"corresponding_institution_ids":["https://openalex.org/I137594350","https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":1.424,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.83090801,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8837131261825562},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7622396945953369},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7040849924087524},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5745367407798767},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5249657034873962},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.5186466574668884},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5013513565063477},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.47346773743629456},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.4517485499382019},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4385963976383209},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.43489930033683777},{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.4271339476108551},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4177093505859375},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38381272554397583},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3057023882865906},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2987246513366699},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.282692551612854},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.20563870668411255},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.14318114519119263},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.13030564785003662}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8837131261825562},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7622396945953369},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7040849924087524},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5745367407798767},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5249657034873962},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.5186466574668884},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5013513565063477},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.47346773743629456},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.4517485499382019},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4385963976383209},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.43489930033683777},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.4271339476108551},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4177093505859375},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38381272554397583},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3057023882865906},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2987246513366699},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.282692551612854},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20563870668411255},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14318114519119263},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.13030564785003662},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mlcad58807.2023.10299859","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mlcad58807.2023.10299859","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W2092377129","https://openalex.org/W2116341502","https://openalex.org/W2126693329","https://openalex.org/W2519887557","https://openalex.org/W2554037413","https://openalex.org/W2792643794","https://openalex.org/W2946332877","https://openalex.org/W2946795101","https://openalex.org/W2964015378","https://openalex.org/W3081295916","https://openalex.org/W3159498079","https://openalex.org/W3203135092","https://openalex.org/W3216272898","https://openalex.org/W4200141518","https://openalex.org/W4293023278","https://openalex.org/W4297733535","https://openalex.org/W4297822317","https://openalex.org/W4312121007","https://openalex.org/W4312121056","https://openalex.org/W4318685693","https://openalex.org/W4385245566","https://openalex.org/W6677316912","https://openalex.org/W6678797189","https://openalex.org/W6739901393","https://openalex.org/W6745537798","https://openalex.org/W6749029207","https://openalex.org/W6843628672"],"related_works":["https://openalex.org/W2498204369","https://openalex.org/W2171413119","https://openalex.org/W4380987687","https://openalex.org/W1557016741","https://openalex.org/W2543290882","https://openalex.org/W2171856294","https://openalex.org/W2139097764","https://openalex.org/W2895905110","https://openalex.org/W1962246972","https://openalex.org/W1964556228"],"abstract_inverted_index":{"Accurate":[0],"timing":[1,24,44,51,81,125,177],"information":[2],"of":[3,142,148,154,168,184,186,197],"a":[4,95,140,151],"digital":[5,56],"design":[6,34,57],"is":[7,39],"available":[8],"only":[9,79],"after":[10],"routing.":[11],"Timing":[12],"violations":[13],"require":[14],"corrective":[15],"changes,":[16],"even":[17],"at":[18,26,193],"the":[19,55,62,69,136,158,194,198],"register-transfer":[20],"level":[21],"(RTL).":[22],"Thus,":[23],"feedback":[25,38],"RTL":[27,70,84,114,121,173,188],"could":[28,189],"guide":[29,190],"micro-architecture":[30,191],"search":[31,192],"and":[32,43,105,124,150,176],"reduce":[33],"iterations.":[35],"However,":[36],"this":[37],"time-consuming,":[40],"requiring":[41],"synthesis":[42,130],"analysis":[45,178],"runs.":[46],"Related":[47],"works":[48],"have":[49],"recognized":[50],"estimations\u2019":[52],"value":[53],"in":[54],"flow.":[58],"Most":[59],"approaches":[60],"use":[61],"pre-routing":[63],"gate-level":[64],"netlist":[65],"as":[66,111],"input,":[67],"losing":[68],"mapping.":[71],"Others":[72],"estimate":[73,94],"either":[74],"individual":[75],"component":[76,103],"delays":[77],"or":[78],"global":[80],"metrics":[82,126],"from":[83,128],"designs.":[85],"This":[86],"paper":[87],"uses":[88],"graph":[89,116],"neural":[90],"networks":[91],"(GNNs)":[92],"to":[93],"design\u2019s":[96],"maximum":[97,152],"arrival":[98],"time":[99],"(AT)":[100],"by":[101,119],"leveraging":[102],"delay":[104],"slew":[106],"prediction.":[107,160],"Our":[108],"approach":[109],"takes":[110],"input":[112],"an":[113,120,187],"intermediate":[115],"representation":[117],"provided":[118],"generation":[122],"tool":[123],"collected":[127],"open-source":[129],"tools.":[131,179],"Experimental":[132],"results":[133],"show":[134],"that":[135],"best":[137],"architecture":[138],"achieves":[139],"coefficient":[141],"determination":[143],"R":[144],"<sup":[145],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[146],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[147],"0.82":[149],"error":[153],"3.79":[155],"ns":[156],"for":[157],"AT":[159],"The":[161],"GNNs":[162],"inference":[163],"runtimes":[164],"are":[165],"three":[166],"orders":[167],"magnitude":[169],"faster":[170],"than":[171],"running":[172],"generation,":[174],"synthesis,":[175],"Fast":[180],"yet":[181],"accurate":[182],"estimations":[183],"ATs":[185],"early":[195],"stages":[196],"design.":[199]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-12T08:34:05.389933","created_date":"2025-10-10T00:00:00"}