{"id":"https://openalex.org/W2483773531","doi":"https://doi.org/10.1109/mixdes.2016.7529732","title":"Encryption using reconfigurable reversible logic gate and its simulation in FPGAs","display_name":"Encryption using reconfigurable reversible logic gate and its simulation in FPGAs","publication_year":2016,"publication_date":"2016-06-01","ids":{"openalex":"https://openalex.org/W2483773531","doi":"https://doi.org/10.1109/mixdes.2016.7529732","mag":"2483773531"},"language":"en","primary_location":{"id":"doi:10.1109/mixdes.2016.7529732","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mixdes.2016.7529732","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077406632","display_name":"Marcin Bryk","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087266","display_name":"Institute of Computer Science","ror":"https://ror.org/003fvp964","country_code":"PL","type":"facility","lineage":["https://openalex.org/I4210087266","https://openalex.org/I99542240"]},{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Marcin Bryk","raw_affiliation_strings":["Institute of Computer Science, Warsaw University of Technology, Warsaw, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487","https://openalex.org/I4210087266"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041757715","display_name":"Krzysztof Gracki","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087266","display_name":"Institute of Computer Science","ror":"https://ror.org/003fvp964","country_code":"PL","type":"facility","lineage":["https://openalex.org/I4210087266","https://openalex.org/I99542240"]},{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Krzysztof Gracki","raw_affiliation_strings":["Institute of Computer Science, Warsaw University of Technology, Warsaw, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487","https://openalex.org/I4210087266"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090536558","display_name":"Pawe\u0142 Kerntopf","orcid":null},"institutions":[{"id":"https://openalex.org/I34250744","display_name":"University of \u0141\u00f3d\u017a","ror":"https://ror.org/05cq64r17","country_code":"PL","type":"education","lineage":["https://openalex.org/I34250744"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Pawel Kerntopf","raw_affiliation_strings":["Faculty of Physics and Applied Informatics', University of L\u00f3d\u017a, L\u00f3d\u017a, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Physics and Applied Informatics', University of L\u00f3d\u017a, L\u00f3d\u017a, Poland","institution_ids":["https://openalex.org/I34250744"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033205887","display_name":"M. Paw\u0142owski","orcid":"https://orcid.org/0000-0003-1658-9799"},"institutions":[{"id":"https://openalex.org/I4210087266","display_name":"Institute of Computer Science","ror":"https://ror.org/003fvp964","country_code":"PL","type":"facility","lineage":["https://openalex.org/I4210087266","https://openalex.org/I99542240"]},{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Marek Pawlowski","raw_affiliation_strings":["Institute of Computer Science, Warsaw University of Technology, Warsaw, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487","https://openalex.org/I4210087266"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000105644","display_name":"Andrzej Skorupski","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087266","display_name":"Institute of Computer Science","ror":"https://ror.org/003fvp964","country_code":"PL","type":"facility","lineage":["https://openalex.org/I4210087266","https://openalex.org/I99542240"]},{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Andrzej Skorupski","raw_affiliation_strings":["Institute of Computer Science, Warsaw University of Technology, Warsaw, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487","https://openalex.org/I4210087266"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5077406632"],"corresponding_institution_ids":["https://openalex.org/I108403487","https://openalex.org/I4210087266"],"apc_list":null,"apc_paid":null,"fwci":0.8834,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.8411075,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"203","last_page":"206"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/toffoli-gate","display_name":"Toffoli gate","score":0.8857117891311646},{"id":"https://openalex.org/keywords/reversible-computing","display_name":"Reversible computing","score":0.6470164656639099},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6445919871330261},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.6174031496047974},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.5961346626281738},{"id":"https://openalex.org/keywords/controlled-not-gate","display_name":"Controlled NOT gate","score":0.5467360019683838},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5386921763420105},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4936157464981079},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4921063780784607},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.47532203793525696},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.44350603222846985},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.41240906715393066},{"id":"https://openalex.org/keywords/quantum-computer","display_name":"Quantum computer","score":0.4101092219352722},{"id":"https://openalex.org/keywords/quantum-gate","display_name":"Quantum gate","score":0.3383004069328308},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.33251380920410156},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32054397463798523},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31444311141967773},{"id":"https://openalex.org/keywords/quantum","display_name":"Quantum","score":0.20392155647277832},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07686099410057068}],"concepts":[{"id":"https://openalex.org/C142465778","wikidata":"https://www.wikidata.org/wiki/Q2502619","display_name":"Toffoli gate","level":5,"score":0.8857117891311646},{"id":"https://openalex.org/C20274610","wikidata":"https://www.wikidata.org/wiki/Q185410","display_name":"Reversible computing","level":4,"score":0.6470164656639099},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6445919871330261},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.6174031496047974},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.5961346626281738},{"id":"https://openalex.org/C182953411","wikidata":"https://www.wikidata.org/wiki/Q917713","display_name":"Controlled NOT gate","level":5,"score":0.5467360019683838},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5386921763420105},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4936157464981079},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4921063780784607},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.47532203793525696},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.44350603222846985},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.41240906715393066},{"id":"https://openalex.org/C58053490","wikidata":"https://www.wikidata.org/wiki/Q176555","display_name":"Quantum computer","level":3,"score":0.4101092219352722},{"id":"https://openalex.org/C58849907","wikidata":"https://www.wikidata.org/wiki/Q2118982","display_name":"Quantum gate","level":4,"score":0.3383004069328308},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.33251380920410156},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32054397463798523},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31444311141967773},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.20392155647277832},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07686099410057068},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mixdes.2016.7529732","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mixdes.2016.7529732","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320311041","display_name":"National Center for Theoretical Sciences","ror":"https://ror.org/02mfp0b67"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1592248844","https://openalex.org/W1965070878","https://openalex.org/W2021257773","https://openalex.org/W2027467269","https://openalex.org/W2042434471","https://openalex.org/W2129731956","https://openalex.org/W2132653113","https://openalex.org/W2152747729","https://openalex.org/W2157574061","https://openalex.org/W2189260785","https://openalex.org/W2912120411","https://openalex.org/W4210451017","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W4289793306","https://openalex.org/W3164207327","https://openalex.org/W3106664074","https://openalex.org/W1590861217","https://openalex.org/W2004061820","https://openalex.org/W4256177326","https://openalex.org/W175446139","https://openalex.org/W1990129337","https://openalex.org/W2010636784","https://openalex.org/W2483773531"],"abstract_inverted_index":{"Recently":[0],"an":[1,62],"approach":[2],"to":[3,39,46],"encryption/decryption":[4,122],"based":[5,50],"on":[6,52],"using":[7,128],"reversible":[8,31,53,70,81,89,104],"logic":[9,32],"circuits":[10,33],"has":[11,91],"been":[12,92],"proposed.":[13,93],"The":[14,94],"reason":[15],"for":[16,121],"this":[17,73,85,141],"is":[18,65,113,126,135],"that":[19],"conventional":[20],"microelectronic":[21],"technologies":[22],"are":[23],"reaching":[24],"their":[25],"limits.":[26],"On":[27],"the":[28,75,116,146],"other":[29],"hand,":[30],"can":[34,78],"decrease":[35],"energy":[36],"dissipation":[37],"theoretically":[38],"zero.":[40],"This":[41],"paper":[42,117],"presents":[43],"a":[44,58,66,87,98,118],"solution":[45,57],"designing":[47],"encryption":[48,63],"schemes":[49],"entirely":[51],"logic.":[54],"In":[55,72,115],"our":[56],"building":[59,76],"block":[60,77],"of":[61,68,96,123,140],"scheme":[64,120,142],"cascade":[67],"4-input":[69],"gates.":[71],"way":[74],"perform":[79],"any":[80],"4-variable":[82],"function.":[83],"For":[84],"purpose":[86],"reconfigurable":[88,99],"gate":[90,100],"design":[95],"such":[97],"built":[101],"from":[102],"standard":[103],"gates,":[105,112],"i.e.":[106],"NOT,":[107],"CNOT,":[108],"Toffoli":[109],"and":[110,131,138],"Fredkin":[111],"presented.":[114],"complete":[119],"8-bit":[124],"data":[125],"described":[127],"VHDL":[129],"language":[130],"its":[132],"quantum":[133],"cost":[134],"calculated.":[136],"Simulation":[137],"verification":[139],"in":[143],"FPGAs":[144],"conclude":[145],"paper.":[147]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-05-20T08:49:12.498775","created_date":"2025-10-10T00:00:00"}