{"id":"https://openalex.org/W2504118667","doi":"https://doi.org/10.1109/mixdes.2016.7529713","title":"A 10-phases programmable clock generator for the application in control of SAR ADC realized in the CMOS 130 nm technology","display_name":"A 10-phases programmable clock generator for the application in control of SAR ADC realized in the CMOS 130 nm technology","publication_year":2016,"publication_date":"2016-06-01","ids":{"openalex":"https://openalex.org/W2504118667","doi":"https://doi.org/10.1109/mixdes.2016.7529713","mag":"2504118667"},"language":"en","primary_location":{"id":"doi:10.1109/mixdes.2016.7529713","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mixdes.2016.7529713","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088770647","display_name":"Rafa\u0142 D\u0142ugosz","orcid":"https://orcid.org/0000-0002-9153-5072"},"institutions":[{"id":"https://openalex.org/I1300393620","display_name":"Bydgoszcz University of Science and Technology","ror":"https://ror.org/049eq0c58","country_code":"PL","type":"education","lineage":["https://openalex.org/I1300393620"]},{"id":"https://openalex.org/I686019","display_name":"AGH University of Krakow","ror":"https://ror.org/00bas1c41","country_code":"PL","type":"education","lineage":["https://openalex.org/I686019"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Rafal Dlugosz","raw_affiliation_strings":["Faculty of Telecommunications, Computer Science and Electrical Engineering ul, UTP University of Science and Technology, Bydgoszcz, Poland"],"affiliations":[{"raw_affiliation_string":"Faculty of Telecommunications, Computer Science and Electrical Engineering ul, UTP University of Science and Technology, Bydgoszcz, Poland","institution_ids":["https://openalex.org/I686019","https://openalex.org/I1300393620"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022889565","display_name":"Tomasz Tala\u015bka","orcid":"https://orcid.org/0000-0001-7252-8013"},"institutions":[{"id":"https://openalex.org/I686019","display_name":"AGH University of Krakow","ror":"https://ror.org/00bas1c41","country_code":"PL","type":"education","lineage":["https://openalex.org/I686019"]},{"id":"https://openalex.org/I1300393620","display_name":"Bydgoszcz University of Science and Technology","ror":"https://ror.org/049eq0c58","country_code":"PL","type":"education","lineage":["https://openalex.org/I1300393620"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Tomasz Talaska","raw_affiliation_strings":["Faculty of Telecommunications, Computer Science and Electrical Engineering ul, UTP University of Science and Technology, Bydgoszcz, Poland"],"affiliations":[{"raw_affiliation_string":"Faculty of Telecommunications, Computer Science and Electrical Engineering ul, UTP University of Science and Technology, Bydgoszcz, Poland","institution_ids":["https://openalex.org/I686019","https://openalex.org/I1300393620"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5088770647"],"corresponding_institution_ids":["https://openalex.org/I1300393620","https://openalex.org/I686019"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07414571,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"37","issue":null,"first_page":"115","last_page":"118"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.8861857652664185},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.65451979637146},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.614041268825531},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6112425923347473},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.5238856673240662},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.5161498785018921},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.5125210285186768},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48864370584487915},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.47250449657440186},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.44285863637924194},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4363178014755249},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.43260523676872253},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4289478659629822},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3191820979118347},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.31777846813201904},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2723780572414398},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21451666951179504},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.1932854950428009},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.18868181109428406},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11125656962394714},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10944259166717529}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.8861857652664185},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.65451979637146},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.614041268825531},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6112425923347473},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5238856673240662},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.5161498785018921},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.5125210285186768},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48864370584487915},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.47250449657440186},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.44285863637924194},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4363178014755249},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.43260523676872253},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4289478659629822},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3191820979118347},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.31777846813201904},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2723780572414398},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21451666951179504},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.1932854950428009},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.18868181109428406},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11125656962394714},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10944259166717529},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mixdes.2016.7529713","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mixdes.2016.7529713","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1569459271","https://openalex.org/W2008640190","https://openalex.org/W2072488539","https://openalex.org/W2101004723","https://openalex.org/W2117311398","https://openalex.org/W2124909075","https://openalex.org/W2418527074","https://openalex.org/W3150096772"],"related_works":["https://openalex.org/W3013924136","https://openalex.org/W2169622190","https://openalex.org/W2224788396","https://openalex.org/W1607003253","https://openalex.org/W2143420037","https://openalex.org/W2118205354","https://openalex.org/W2615366277","https://openalex.org/W2151256709","https://openalex.org/W4238381000","https://openalex.org/W2377552037"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3,45,79],"present":[4],"a":[5,129],"10-phases":[6],"programmable":[7,41],"clock":[8,34,51,115,124],"generator":[9,116],"for":[10],"the":[11,25,48,68,95,99,111,120,123],"application":[12],"in":[13,24,72,102,110],"control":[14,119],"of":[15,50,97,122],"Successive":[16],"Approximation":[17],"Register":[18],"(SAR)":[19],"Analog-to-Digital":[20],"Converters":[21],"(ADC),":[22],"realized":[23],"CMOS":[26],"130":[27],"nm":[28],"technology.":[29],"The":[30,40,57,114],"circuit":[31,58],"provides":[32],"10":[33],"signals":[35],"on":[36,83],"separate":[37],"terminals":[38,84],"(sections).":[39],"feature":[42,90],"means":[43],"that":[44],"can":[46,80,106],"program":[47],"number":[49],"phases":[52],"which":[53,63,103,126],"are":[54,65,77],"cyclically":[55],"repeated.":[56],"allows":[59,117],"also":[60,107,128],"to":[61,118],"select":[62],"sections":[64],"used":[66],"at":[67],"moment.":[69],"For":[70],"example,":[71],"case":[73],"if":[74],"only":[75],"6-phases":[76],"needed,":[78],"obtain":[81],"them":[82],"1-6,":[85],"2-7,":[86],"...,":[87],"5-10.":[88],"This":[89],"is":[91,127],"important":[92],"looking":[93],"from":[94],"point":[96],"view":[98],"SAR":[100],"ADC,":[101],"corresponding":[104],"branches":[105],"be":[108],"selected":[109],"same":[112],"way.":[113],"width":[121],"phases,":[125],"useful":[130],"feature.":[131]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}