{"id":"https://openalex.org/W1603849427","doi":"https://doi.org/10.1109/mixdes.2015.7208538","title":"IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology","display_name":"IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1603849427","doi":"https://doi.org/10.1109/mixdes.2015.7208538","mag":"1603849427"},"language":"en","primary_location":{"id":"doi:10.1109/mixdes.2015.7208538","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mixdes.2015.7208538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044367039","display_name":"Mariusz Derlecki","orcid":null},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Mariusz Derlecki","raw_affiliation_strings":["Institute of Microelectronics & Optoelectronics, Warsaw University of Technology ul. Koszykowa 75, 00-662 Warszawa, Poland","Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics & Optoelectronics, Warsaw University of Technology ul. Koszykowa 75, 00-662 Warszawa, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, Poland","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051716219","display_name":"Tomasz Borejko","orcid":"https://orcid.org/0000-0003-4853-3933"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Tomasz Borejko","raw_affiliation_strings":["Institute of Microelectronics & Optoelectronics, Warsaw University of Technology ul. Koszykowa 75, 00-662 Warszawa, Poland","Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics & Optoelectronics, Warsaw University of Technology ul. Koszykowa 75, 00-662 Warszawa, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, Poland","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056589147","display_name":"Witold A. Pleskacz","orcid":"https://orcid.org/0000-0001-7064-503X"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Witold A. Pleskacz","raw_affiliation_strings":["Institute of Microelectronics & Optoelectronics, Warsaw University of Technology ul. Koszykowa 75, 00-662 Warszawa, Poland","Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics & Optoelectronics, Warsaw University of Technology ul. Koszykowa 75, 00-662 Warszawa, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, Poland","institution_ids":["https://openalex.org/I108403487"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5044367039"],"corresponding_institution_ids":["https://openalex.org/I108403487"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02910373,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"334","last_page":"338"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.7835463881492615},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.618939220905304},{"id":"https://openalex.org/keywords/butterworth-filter","display_name":"Butterworth filter","score":0.5939303636550903},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.5443480014801025},{"id":"https://openalex.org/keywords/polyphase-system","display_name":"Polyphase system","score":0.541715681552887},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.4881218373775482},{"id":"https://openalex.org/keywords/active-filter","display_name":"Active filter","score":0.48714253306388855},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.48139262199401855},{"id":"https://openalex.org/keywords/voltage-controlled-filter","display_name":"Voltage-controlled filter","score":0.4653265178203583},{"id":"https://openalex.org/keywords/high-pass-filter","display_name":"High-pass filter","score":0.4529402256011963},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.4464784562587738},{"id":"https://openalex.org/keywords/low-pass-filter","display_name":"Low-pass filter","score":0.44318148493766785},{"id":"https://openalex.org/keywords/electronic-filter-topology","display_name":"Electronic filter topology","score":0.43676233291625977},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4249560832977295},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.39519232511520386},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.3838672935962677},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3569537401199341},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.299121618270874},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27198395133018494},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15773585438728333},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1568467915058136},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.06876996159553528}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.7835463881492615},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.618939220905304},{"id":"https://openalex.org/C70757512","wikidata":"https://www.wikidata.org/wiki/Q1018162","display_name":"Butterworth filter","level":5,"score":0.5939303636550903},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.5443480014801025},{"id":"https://openalex.org/C96157337","wikidata":"https://www.wikidata.org/wiki/Q391639","display_name":"Polyphase system","level":2,"score":0.541715681552887},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.4881218373775482},{"id":"https://openalex.org/C85899133","wikidata":"https://www.wikidata.org/wiki/Q557211","display_name":"Active filter","level":3,"score":0.48714253306388855},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.48139262199401855},{"id":"https://openalex.org/C126955663","wikidata":"https://www.wikidata.org/wiki/Q1638353","display_name":"Voltage-controlled filter","level":5,"score":0.4653265178203583},{"id":"https://openalex.org/C156137958","wikidata":"https://www.wikidata.org/wiki/Q262754","display_name":"High-pass filter","level":4,"score":0.4529402256011963},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.4464784562587738},{"id":"https://openalex.org/C44682112","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Low-pass filter","level":3,"score":0.44318148493766785},{"id":"https://openalex.org/C26441681","wikidata":"https://www.wikidata.org/wiki/Q5358359","display_name":"Electronic filter topology","level":5,"score":0.43676233291625977},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4249560832977295},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.39519232511520386},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3838672935962677},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3569537401199341},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.299121618270874},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27198395133018494},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15773585438728333},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1568467915058136},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.06876996159553528}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mixdes.2015.7208538","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mixdes.2015.7208538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W128723314","https://openalex.org/W1806313618","https://openalex.org/W1990749651","https://openalex.org/W2033656029","https://openalex.org/W2340429540","https://openalex.org/W2785684286","https://openalex.org/W4231501498","https://openalex.org/W6638176053","https://openalex.org/W6748128889"],"related_works":["https://openalex.org/W3201109635","https://openalex.org/W26706577","https://openalex.org/W2143111556","https://openalex.org/W2051335759","https://openalex.org/W4244992685","https://openalex.org/W2739282933","https://openalex.org/W2150714587","https://openalex.org/W1492592725","https://openalex.org/W2182158460","https://openalex.org/W4318601934"],"abstract_inverted_index":{"This":[0,15],"paper":[1],"presents":[2],"a":[3,21],"sixth-order":[4],"IF":[5],"polyphase":[6],"band-pass":[7],"filter":[8,16,24,90],"design":[9],"in":[10,48,95],"28":[11],"nm":[12],"FD-SOI":[13],"technology.":[14],"has":[17,57],"been":[18,58,65,93],"synthesized":[19],"from":[20],"low-pass":[22],"Butterworth":[23],"prototype.":[25],"The":[26,61,78,84],"filter's":[27],"bandwidth":[28],"is":[29,36,46,81],"1.2":[30],"MHz":[31],"and":[32,75],"its":[33],"center":[34],"frequency":[35],"2":[37],"MHz.":[38],"A":[39],"calibration":[40],"technique":[41],"using":[42,67],"back-gate":[43],"biasing":[44],"that":[45],"available":[47],"fully":[49],"depleted":[50],"SOI":[51],"to":[52],"minimize":[53],"the":[54,88],"mismatch":[55],"impact,":[56],"also":[59,92],"described.":[60],"two":[62,68],"filters":[63],"have":[64,91],"designed":[66,89],"different":[69],"types":[70],"of":[71,87],"transistors":[72],"(regular":[73],"P/NMOS":[74],"flip-well":[76],"P/NMOS).":[77],"power":[79],"consumption":[80],"1.4":[82],"mW.":[83],"simulation":[85],"results":[86],"presented":[94],"this":[96],"paper.":[97]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}