{"id":"https://openalex.org/W1991986865","doi":"https://doi.org/10.1109/mixdes.2014.6872176","title":"A self-calibration technique for fast-switching frequency-hopped UWB synthesis","display_name":"A self-calibration technique for fast-switching frequency-hopped UWB synthesis","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W1991986865","doi":"https://doi.org/10.1109/mixdes.2014.6872176","mag":"1991986865"},"language":"en","primary_location":{"id":"doi:10.1109/mixdes.2014.6872176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mixdes.2014.6872176","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070746864","display_name":"Amin Ojani","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Amin Ojani","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden","Dept. of Electr. Eng. Linkoping Univ. Link\u00f6ping Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"Dept. of Electr. Eng. Linkoping Univ. Link\u00f6ping Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047313116","display_name":"Behzad Mesgarzadeh","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Behzad Mesgarzadeh","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden","Dept. of Electr. Eng. Linkoping Univ. Link\u00f6ping Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"Dept. of Electr. Eng. Linkoping Univ. Link\u00f6ping Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029147977","display_name":"Atila Alvandpour","orcid":"https://orcid.org/0000-0001-8922-2360"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Atila Alvandpour","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden","Dept. of Electr. Eng. Linkoping Univ. Link\u00f6ping Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"Dept. of Electr. Eng. Linkoping Univ. Link\u00f6ping Sweden","institution_ids":["https://openalex.org/I102134673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I102134673"],"apc_list":null,"apc_paid":null,"fwci":0.4079,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.48691922,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"154","last_page":"159"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5979795455932617},{"id":"https://openalex.org/keywords/settling-time","display_name":"Settling time","score":0.5919294357299805},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5816832184791565},{"id":"https://openalex.org/keywords/sideband","display_name":"Sideband","score":0.5764704942703247},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.5735384225845337},{"id":"https://openalex.org/keywords/switching-time","display_name":"Switching time","score":0.567866861820221},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.4981577396392822},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4771694242954254},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.46992409229278564},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.44273343682289124},{"id":"https://openalex.org/keywords/wideband","display_name":"Wideband","score":0.434325635433197},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.4048137068748474},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.364422082901001},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.32358255982398987},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2430696189403534},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.18534207344055176},{"id":"https://openalex.org/keywords/radio-frequency","display_name":"Radio frequency","score":0.16138914227485657}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5979795455932617},{"id":"https://openalex.org/C14781684","wikidata":"https://www.wikidata.org/wiki/Q3983320","display_name":"Settling time","level":3,"score":0.5919294357299805},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5816832184791565},{"id":"https://openalex.org/C2776499502","wikidata":"https://www.wikidata.org/wiki/Q2267009","display_name":"Sideband","level":3,"score":0.5764704942703247},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.5735384225845337},{"id":"https://openalex.org/C199310435","wikidata":"https://www.wikidata.org/wiki/Q7659121","display_name":"Switching time","level":2,"score":0.567866861820221},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.4981577396392822},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4771694242954254},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.46992409229278564},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.44273343682289124},{"id":"https://openalex.org/C2780202535","wikidata":"https://www.wikidata.org/wiki/Q4524457","display_name":"Wideband","level":2,"score":0.434325635433197},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4048137068748474},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.364422082901001},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.32358255982398987},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2430696189403534},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.18534207344055176},{"id":"https://openalex.org/C74064498","wikidata":"https://www.wikidata.org/wiki/Q3396184","display_name":"Radio frequency","level":2,"score":0.16138914227485657},{"id":"https://openalex.org/C160030872","wikidata":"https://www.wikidata.org/wiki/Q2142864","display_name":"Step response","level":2,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mixdes.2014.6872176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mixdes.2014.6872176","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1608321057","https://openalex.org/W1677884181","https://openalex.org/W2040464170","https://openalex.org/W2058316471","https://openalex.org/W2079753196","https://openalex.org/W2115320563","https://openalex.org/W2156640525","https://openalex.org/W2161455871","https://openalex.org/W2169190898","https://openalex.org/W2178774287","https://openalex.org/W6636244958","https://openalex.org/W6665108139","https://openalex.org/W6683048372"],"related_works":["https://openalex.org/W2166555237","https://openalex.org/W2622028395","https://openalex.org/W2161572852","https://openalex.org/W4386197759","https://openalex.org/W2389258116","https://openalex.org/W2393010087","https://openalex.org/W2043438372","https://openalex.org/W2160364955","https://openalex.org/W4312410307","https://openalex.org/W2122557123"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,7,40,44,119,173,183],"self-calibration":[4],"technique":[5,26],"for":[6],"fast-switching":[8,114],"DLL-based":[9],"frequency":[10],"synthesizer":[11,165],"targeting":[12],"frequency-hopped":[13],"ultra-wideband":[14],"(UWB)":[15],"communication.":[16],"The":[17,167],"proposed":[18,113,168],"architecture":[19,169],"employs":[20],"the":[21,29,48,52,56,62,93,96,108,112,123,130,134,145,151,164,179],"concept":[22],"of":[23,73,107,154,188],"track-and-hold":[24],"(T/H)":[25],"to":[27,61,68,91,158,163],"sample":[28],"lock":[30],"control":[31,135],"voltages":[32,58,98],"regarding":[33],"each":[34],"channel":[35,71,101],"and":[36,84,104,133,178],"store":[37],"them":[38],"across":[39],"corresponding":[41],"capacitor":[42],"during":[43],"start-up":[45],"phase.":[46],"During":[47],"normal":[49],"operation":[50],"when":[51],"hopping":[53],"command":[54],"arrives,":[55],"stored":[57],"are":[59,87],"applied":[60],"loop":[63,121],"in":[64,89,95,126,139,150,172],"an":[65],"open-loop":[66],"regime":[67],"perform":[69],"fast":[70],"switching":[72,186],"sub-9.5":[74],"ns":[75],"which":[76],"is":[77,142,170],"required":[78],"by":[79,100],"WiMedia-UWB":[80],"standard.":[81],"Certain":[82],"architectural":[83],"circuit":[85],"methods":[86],"utilized":[88],"order":[90],"minimize":[92],"error":[94],"sampled":[97],"caused":[99],"charge":[102],"injection":[103],"clock":[105],"feedthrough":[106],"sampling":[109],"switches.":[110],"Since":[111],"scheme":[115],"does":[116],"not":[117],"require":[118],"wide":[120],"bandwidth,":[122],"existing":[124],"tradeoff":[125],"phase-locked":[127],"systems":[128],"between":[129],"settling":[131],"time":[132,187],"voltage":[136],"ripples":[137],"resulting":[138],"sideband":[140],"spurs":[141],"eliminated.":[143],"Moreover,":[144],"VCDL":[146],"can":[147],"be":[148],"biased":[149],"low-gain":[152],"region":[153],"its":[155,160],"transfer":[156,162],"function":[157],"reduce":[159],"noise":[161],"output.":[166],"implemented":[171],"65-nm":[174],"standard":[175],"CMOS":[176],"process":[177],"simulation":[180],"results":[181],"indicate":[182],"worst-case":[184],"band":[185],"less":[189],"than":[190],"5.5":[191],"ns.":[192]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}