{"id":"https://openalex.org/W4244668938","doi":"https://doi.org/10.1109/micro.2016.7783749","title":"Efficient data supply for hardware accelerators with prefetching and access/execute decoupling","display_name":"Efficient data supply for hardware accelerators with prefetching and access/execute decoupling","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W4244668938","doi":"https://doi.org/10.1109/micro.2016.7783749"},"language":"en","primary_location":{"id":"doi:10.1109/micro.2016.7783749","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.2016.7783749","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100357750","display_name":"Tao Chen","orcid":"https://orcid.org/0000-0002-4980-6836"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Tao Chen","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024329178","display_name":"G. Edward Suh","orcid":"https://orcid.org/0000-0001-6409-9888"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Edward Suh","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100357750"],"corresponding_institution_ids":["https://openalex.org/I205783295"],"apc_list":null,"apc_paid":null,"fwci":1.892,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.86279857,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.841238260269165},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.600272536277771},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5099784135818481},{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.49262553453445435},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.4833630919456482},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.47933492064476013},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.456851065158844},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.45248183608055115},{"id":"https://openalex.org/keywords/decoupling","display_name":"Decoupling (probability)","score":0.430691659450531},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4164765477180481},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35737696290016174},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3372325301170349},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2700500786304474},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.09180271625518799}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.841238260269165},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.600272536277771},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5099784135818481},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.49262553453445435},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.4833630919456482},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.47933492064476013},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.456851065158844},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.45248183608055115},{"id":"https://openalex.org/C205606062","wikidata":"https://www.wikidata.org/wiki/Q5249645","display_name":"Decoupling (probability)","level":2,"score":0.430691659450531},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4164765477180481},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35737696290016174},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3372325301170349},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2700500786304474},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.09180271625518799},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/micro.2016.7783749","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.2016.7783749","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7099999785423279,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337345","display_name":"Office of Naval Research","ror":"https://ror.org/00rk2pe57"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W2012114780","https://openalex.org/W2022128349","https://openalex.org/W2024612992","https://openalex.org/W2033493263","https://openalex.org/W2066443755","https://openalex.org/W2074041401","https://openalex.org/W2078017054","https://openalex.org/W2079751107","https://openalex.org/W2079790908","https://openalex.org/W2092741255","https://openalex.org/W2099958604","https://openalex.org/W2112678088","https://openalex.org/W2122078405","https://openalex.org/W2123608497","https://openalex.org/W2130408605","https://openalex.org/W2147657366","https://openalex.org/W2152839228","https://openalex.org/W2152944133","https://openalex.org/W2154790323","https://openalex.org/W2162385899","https://openalex.org/W2167008350","https://openalex.org/W2171006257","https://openalex.org/W2171546589","https://openalex.org/W2237339430","https://openalex.org/W2239894058","https://openalex.org/W2537450429","https://openalex.org/W3138241115","https://openalex.org/W3147011727","https://openalex.org/W4231131543","https://openalex.org/W4236433846","https://openalex.org/W4241148135","https://openalex.org/W6672033296","https://openalex.org/W6696642037"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2027972911","https://openalex.org/W2157978810","https://openalex.org/W2532502681","https://openalex.org/W2168956691"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,78,133],"architecture":[4,138],"framework":[5,83,105,131],"to":[6,39,60,66,69,94,108],"easily":[7],"design":[8],"hardware":[9,114],"accelerators":[10,26,55,155],"that":[11,113,145],"can":[12,116,149],"effectively":[13,117],"tolerate":[14],"long":[15],"and":[16,22,43,77,97,163],"variable":[17],"memory":[18,76,110,128],"latency":[19],"using":[20,139],"prefetching":[21,96,115],"access/execute":[23,98,137],"decoupling.":[24],"Hardware":[25],"are":[27],"becoming":[28],"increasingly":[29],"popular":[30],"in":[31,62],"modern":[32],"computing":[33],"systems":[34],"as":[35],"a":[36],"promising":[37],"approach":[38],"achieve":[40],"higher":[41],"performance":[42,152],"energy":[44,166],"efficiency":[45],"when":[46],"technology":[47],"scaling":[48],"is":[49],"slowing":[50],"down.":[51],"However,":[52],"today's":[53],"high-performance":[54],"require":[56],"significant":[57],"manual":[58,102],"efforts":[59],"design,":[61],"large":[63],"part":[64],"due":[65],"the":[67,81,130,146],"need":[68],"carefully":[70],"orchestrate":[71],"data":[72,119],"transfers":[73],"between":[74],"external":[75],"accelerator.":[79],"Instead,":[80],"proposed":[82,147],"utilizes":[84],"automated":[85],"program":[86,140],"analysis":[87],"along":[88],"with":[89,100,122,135],"High-Level":[90],"Synthesis":[91],"(HLS)":[92],"tools":[93],"enable":[95],"decoupling":[99],"minimal":[101],"efforts.":[103],"The":[104],"adds":[106],"tags":[107],"accelerator":[109,134],"accesses":[111,121],"so":[112],"preload":[118],"for":[120],"regular":[123],"patterns.":[124],"To":[125],"handle":[126],"irregular":[127],"accesses,":[129],"generates":[132],"decoupled":[136],"slicing.":[141],"Experimental":[142],"results":[143],"show":[144],"optimizations":[148],"significantly":[150],"improve":[151],"of":[153,158,169],"HLS-generated":[154],"(average":[156,168],"speedup":[157],"2.28x":[159],"across":[160],"eight":[161],"accelerators)":[162],"often":[164],"reduce":[165],"consumption":[167],"15%).":[170]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}