{"id":"https://openalex.org/W4229602664","doi":"https://doi.org/10.1109/micro.2016.7783739","title":"C<sup>3</sup>D: Mitigating the NUMA bottleneck via coherent DRAM caches","display_name":"C<sup>3</sup>D: Mitigating the NUMA bottleneck via coherent DRAM caches","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W4229602664","doi":"https://doi.org/10.1109/micro.2016.7783739"},"language":"en","primary_location":{"id":"doi:10.1109/micro.2016.7783739","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.2016.7783739","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://www.research.ed.ac.uk/en/publications/8c12524f-a6af-4eb6-a59e-9b3e87a9a858","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014432716","display_name":"Cheng\u2010Chieh Huang","orcid":"https://orcid.org/0000-0002-1819-8989"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Cheng-Chieh Huang","raw_affiliation_strings":["Institute of Computing Systems Architecture, University of Edinburgh"],"affiliations":[{"raw_affiliation_string":"Institute of Computing Systems Architecture, University of Edinburgh","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017675158","display_name":"Rakesh Kumar","orcid":"https://orcid.org/0000-0001-6306-304X"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Rakesh Kumar","raw_affiliation_strings":["Institute of Computing Systems Architecture, University of Edinburgh"],"affiliations":[{"raw_affiliation_string":"Institute of Computing Systems Architecture, University of Edinburgh","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023429942","display_name":"Marco Elver","orcid":"https://orcid.org/0000-0002-1747-8399"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Marco Elver","raw_affiliation_strings":["Institute of Computing Systems Architecture, University of Edinburgh"],"affiliations":[{"raw_affiliation_string":"Institute of Computing Systems Architecture, University of Edinburgh","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010276850","display_name":"Boris Grot","orcid":"https://orcid.org/0000-0001-6525-0762"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Boris Grot","raw_affiliation_strings":["Institute of Computing Systems Architecture, University of Edinburgh"],"affiliations":[{"raw_affiliation_string":"Institute of Computing Systems Architecture, University of Edinburgh","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056071760","display_name":"Vijay Nagarajan","orcid":"https://orcid.org/0009-0000-5045-4754"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Vijay Nagarajan","raw_affiliation_strings":["Institute of Computing Systems Architecture, University of Edinburgh"],"affiliations":[{"raw_affiliation_string":"Institute of Computing Systems Architecture, University of Edinburgh","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5014432716"],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":0.97,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.77233245,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8466160297393799},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.8211524486541748},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7643773555755615},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6444419026374817},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.6359710097312927},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5783937573432922},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5185607075691223},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.49257975816726685},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.47553157806396484},{"id":"https://openalex.org/keywords/directory","display_name":"Directory","score":0.45991742610931396},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4585343301296234},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.43306222558021545},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.42924246191978455},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.37169572710990906},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.35605233907699585},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3451099991798401},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34046271443367004},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33920127153396606},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3226650059223175},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.30020156502723694},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.1926122009754181},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.17739450931549072}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8466160297393799},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.8211524486541748},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7643773555755615},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6444419026374817},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.6359710097312927},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5783937573432922},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5185607075691223},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.49257975816726685},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.47553157806396484},{"id":"https://openalex.org/C2777683733","wikidata":"https://www.wikidata.org/wiki/Q201456","display_name":"Directory","level":2,"score":0.45991742610931396},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4585343301296234},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.43306222558021545},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.42924246191978455},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.37169572710990906},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.35605233907699585},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3451099991798401},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34046271443367004},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33920127153396606},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3226650059223175},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.30020156502723694},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.1926122009754181},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.17739450931549072},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/micro.2016.7783739","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.2016.7783739","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.ed.ac.uk:openaire/8c12524f-a6af-4eb6-a59e-9b3e87a9a858","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/8c12524f-a6af-4eb6-a59e-9b3e87a9a858","pdf_url":null,"source":{"id":"https://openalex.org/S4306400321","display_name":"Edinburgh Research Explorer (University of Edinburgh)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98677209","host_organization_name":"University of Edinburgh","host_organization_lineage":["https://openalex.org/I98677209"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Huang, C-C, Kumar, R, Elver, M, Grot, B & Nagarajan, V 2016, C3D: Mitigating the NUMA Bottleneck via Coherent DRAM Caches. in Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium on. Institute of Electrical and Electronics Engineers, Taipei, Taiwan, 49th Annual IEEE/ACM International Symposium on Microarchitecture, Taipei, Taiwan, Province of China, 15/10/16. https://doi.org/10.1109/MICRO.2016.7783739","raw_type":"contributionToPeriodical"},{"id":"pmh:oai:pure.ed.ac.uk:publications/8c12524f-a6af-4eb6-a59e-9b3e87a9a858","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/document/7783739/","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""},{"id":"pmh:oai:pure.ed.ac.uk:publications/8c12524f-a6af-4eb6-a59e-9b3e87a9a858","is_oa":true,"landing_page_url":"https://hdl.handle.net/20.500.11820/8c12524f-a6af-4eb6-a59e-9b3e87a9a858","pdf_url":null,"source":{"id":"https://openalex.org/S4306400321","display_name":"Edinburgh Research Explorer (University of Edinburgh)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98677209","host_organization_name":"University of Edinburgh","host_organization_lineage":["https://openalex.org/I98677209"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Huang, C-C, Kumar, R, Elver, M, Grot, B & Nagarajan, V 2016, C3D: Mitigating the NUMA Bottleneck via Coherent DRAM Caches. in Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium on. Institute of Electrical and Electronics Engineers, Taipei, Taiwan, 49th Annual IEEE/ACM International Symposium on Microarchitecture, Taipei, Taiwan, Province of China, 15/10/16. https://doi.org/10.1109/MICRO.2016.7783739","raw_type":"contributionToPeriodical"}],"best_oa_location":{"id":"pmh:oai:pure.ed.ac.uk:openaire/8c12524f-a6af-4eb6-a59e-9b3e87a9a858","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/8c12524f-a6af-4eb6-a59e-9b3e87a9a858","pdf_url":null,"source":{"id":"https://openalex.org/S4306400321","display_name":"Edinburgh Research Explorer (University of Edinburgh)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98677209","host_organization_name":"University of Edinburgh","host_organization_lineage":["https://openalex.org/I98677209"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Huang, C-C, Kumar, R, Elver, M, Grot, B & Nagarajan, V 2016, C3D: Mitigating the NUMA Bottleneck via Coherent DRAM Caches. in Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium on. Institute of Electrical and Electronics Engineers, Taipei, Taiwan, 49th Annual IEEE/ACM International Symposium on Microarchitecture, Taipei, Taiwan, Province of China, 15/10/16. https://doi.org/10.1109/MICRO.2016.7783739","raw_type":"contributionToPeriodical"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5600000023841858,"display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G1838753993","display_name":null,"funder_award_id":"EP/M001202/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G2316399547","display_name":null,"funder_award_id":"EP/M027317/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W35708471","https://openalex.org/W1663509712","https://openalex.org/W1769402780","https://openalex.org/W1977349283","https://openalex.org/W1979978831","https://openalex.org/W1981951650","https://openalex.org/W1993254370","https://openalex.org/W1995287338","https://openalex.org/W2023972921","https://openalex.org/W2029764709","https://openalex.org/W2036403064","https://openalex.org/W2046996113","https://openalex.org/W2050487400","https://openalex.org/W2074113453","https://openalex.org/W2082982763","https://openalex.org/W2115716046","https://openalex.org/W2120635877","https://openalex.org/W2120829734","https://openalex.org/W2122100378","https://openalex.org/W2126188898","https://openalex.org/W2139397536","https://openalex.org/W2141181087","https://openalex.org/W2141686508","https://openalex.org/W2147743629","https://openalex.org/W2148103955","https://openalex.org/W2148797773","https://openalex.org/W2151032144","https://openalex.org/W2151233837","https://openalex.org/W2152933730","https://openalex.org/W2157802978","https://openalex.org/W2169865228","https://openalex.org/W2169875292","https://openalex.org/W2170241157","https://openalex.org/W4238182192","https://openalex.org/W4239813889","https://openalex.org/W4243577185","https://openalex.org/W4254918363","https://openalex.org/W4312364354","https://openalex.org/W6680569787"],"related_works":["https://openalex.org/W2555826082","https://openalex.org/W3008068282","https://openalex.org/W4288804802","https://openalex.org/W4293430534","https://openalex.org/W4297812927","https://openalex.org/W2335743642","https://openalex.org/W2896161911","https://openalex.org/W2185658074","https://openalex.org/W2800412005","https://openalex.org/W4285245242"],"abstract_inverted_index":{"Massive":[0],"datasets":[1],"prevalent":[2],"in":[3,47,63,66,210,246],"scale-out,":[4],"enterprise,":[5],"and":[6,24,33,125,170],"high-performance":[7],"computing":[8],"are":[9],"driving":[10],"a":[11,58,194,199,202,215,247,251],"trend":[12],"toward":[13],"ever-larger":[14],"memory":[15,22,41,56,94,155],"capacities":[16],"per":[17,27],"node.":[18],"To":[19,96],"satisfy":[20],"the":[21,51,84,117,132,189,211,222],"demands":[23],"maximize":[25],"performance":[26,65,243],"unit":[28],"cost,":[29],"today's":[30],"commodity":[31],"HPC":[32],"server":[34],"nodes":[35],"tend":[36],"to":[37,90,105,108,148,176,191,241],"feature":[38],"multi-socket":[39],"shared":[40,70],"NUMA":[42,85],"organizations.":[43],"An":[44],"important":[45],"problem":[46],"these":[48,99,177,239],"designs":[49],"is":[50],"high":[52,133,141],"latency":[53,135],"of":[54,92,111,119,127,136],"accessing":[55],"on":[57,180,198],"remote":[59,93,112,149,195],"socket":[60,107],"that":[61,77,206],"results":[62],"degraded":[64],"workloads":[67],"with":[68,116,140,167],"large":[69],"data":[71],"working":[72],"sets.":[73],"This":[74],"work":[75],"shows":[76],"emerging":[78],"DRAM":[79,100,128,137,150,185,196,212,231,254],"caches":[80,101,151,166,186],"can":[81,145],"help":[82],"mitigate":[83],"bottleneck":[86],"by":[87,244],"filtering":[88],"up":[89],"98%":[91],"accesses.":[95,156],"be":[97,103],"effective,":[98],"must":[102],"private":[104],"each":[106],"allow":[109],"caching":[110],"memory,":[113],"which":[114],"comes":[115],"challenge":[118,159],"ensuring":[120],"coherence":[121,161,220],"across":[122],"multiple":[123],"sockets":[124],"GBs":[126],"cache":[129,197,213],"capacity.":[130,173],"Moreover,":[131],"access":[134,193],"caches,":[138],"combined":[139],"inter-socket":[142],"communication":[143],"latencies,":[144],"make":[146],"hits":[147,169],"slower":[152],"than":[153],"main":[154],"These":[157],"features":[158],"existing":[160],"protocols":[162],"optimized":[163],"for":[164,218],"on-chip":[165,204],"fast":[168],"modest":[171],"storage":[172],"Our":[174,226],"solution":[175],"challenges":[178],"relies":[179],"two":[181],"insights.":[182],"First,":[183],"keeping":[184],"clean":[187],"avoids":[188,207],"need":[190],"ever":[192],"read.":[200],"Second,":[201],"non-inclusive":[203],"directory":[205,224],"tracking":[208],"blocks":[209],"enables":[214],"light-weight":[216],"protocol":[217],"guaranteeing":[219],"without":[221,253],"staggering":[223],"costs.":[225],"design,":[227],"called":[228],"Clean":[229],"Coherent":[230],"Caches":[232],"(C":[233],"<sup":[234],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[235],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">3</sup>":[236],"D),":[237],"leverages":[238],"insights":[240],"improve":[242],"6.4-50.7%":[245],"quad-socket":[248],"system":[249],"versus":[250],"baseline":[252],"caches.":[255]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-03T22:45:19.894376","created_date":"2025-10-10T00:00:00"}