{"id":"https://openalex.org/W4250401973","doi":"https://doi.org/10.1109/micro.2003.1253182","title":"TLC: transmission line caches","display_name":"TLC: transmission line caches","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W4250401973","doi":"https://doi.org/10.1109/micro.2003.1253182"},"language":"en","primary_location":{"id":"doi:10.1109/micro.2003.1253182","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.2003.1253182","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077056823","display_name":"Bradford M. Beckmann","orcid":"https://orcid.org/0000-0002-5444-6521"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B.M. Beckmann","raw_affiliation_strings":["University of Wisconsin","Computer Sciences Department, University of Wisconsin, Madison, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin","institution_ids":[]},{"raw_affiliation_string":"Computer Sciences Department, University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075888890","display_name":"David A. Wood","orcid":"https://orcid.org/0000-0002-9748-8561"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.A. Wood","raw_affiliation_strings":["University of Wisconsin","Computer Sciences Department, University of Wisconsin, Madison, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin","institution_ids":[]},{"raw_affiliation_string":"Computer Sciences Department, University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":2.2733,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.90722507,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"43","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7505230903625488},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6271150708198547},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5828372836112976},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5181006789207458},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5091096758842468},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4805203378200531},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.394826740026474},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.29242753982543945},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15029001235961914},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13859152793884277},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12152093648910522}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7505230903625488},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6271150708198547},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5828372836112976},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5181006789207458},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5091096758842468},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4805203378200531},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.394826740026474},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.29242753982543945},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15029001235961914},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13859152793884277},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12152093648910522}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/micro.2003.1253182","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.2003.1253182","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W1544623790","https://openalex.org/W1615395211","https://openalex.org/W1971787567","https://openalex.org/W1986535055","https://openalex.org/W1995939557","https://openalex.org/W2006097283","https://openalex.org/W2039358455","https://openalex.org/W2048583641","https://openalex.org/W2049389210","https://openalex.org/W2090694109","https://openalex.org/W2104844464","https://openalex.org/W2105844603","https://openalex.org/W2120635877","https://openalex.org/W2126372249","https://openalex.org/W2127419850","https://openalex.org/W2133985894","https://openalex.org/W2138351227","https://openalex.org/W2147374953","https://openalex.org/W2152155746","https://openalex.org/W2153517788","https://openalex.org/W2158561130","https://openalex.org/W2160401437","https://openalex.org/W2162109942","https://openalex.org/W2163686347","https://openalex.org/W2164944039","https://openalex.org/W2169468042","https://openalex.org/W2171825402","https://openalex.org/W2543356528","https://openalex.org/W4235990555","https://openalex.org/W4245640831","https://openalex.org/W4248492382","https://openalex.org/W4253421865","https://openalex.org/W4255982026","https://openalex.org/W6602613798","https://openalex.org/W6662922982","https://openalex.org/W6675224354","https://openalex.org/W6683418528"],"related_works":["https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2766970861","https://openalex.org/W3125341812","https://openalex.org/W1991674760","https://openalex.org/W1668171714","https://openalex.org/W2155297398","https://openalex.org/W4380607112","https://openalex.org/W2218294330","https://openalex.org/W2018755015"],"abstract_inverted_index":{"It":[0],"is":[1,51],"widely":[2],"accepted":[3],"that":[4,31,127,191],"the":[5,85,95,132,137,145,150,158,198],"disproportionate":[6],"scaling":[7],"of":[8,78,97,121,167,205],"transistor":[9],"and":[10,35,156,219],"conventional":[11,65],"on-chip":[12,36,55,115],"interconnect":[13],"performance":[14,22,175,196],"presents":[15],"a":[16,76,98,119,202],"major":[17],"barrier":[18],"to":[19,39,48,52,59,64,75,111,136],"future":[20],"high":[21],"systems.":[23],"Previous":[24],"research":[25],"has":[26],"focused":[27],"on":[28],"wire-centric":[29],"designs":[30,126,172],"use":[32],"parallelism,":[33],"locality,":[34],"wiring":[37],"bandwidth":[38],"compensate":[40],"for":[41,80,87],"long":[42],"wire":[43],"latency.":[44,62],"An":[45],"alternative":[46],"approach":[47],"this":[49,90,104],"problem":[50],"exploit":[53],"newly-emerging":[54],"transmission":[56,68,109,122,178],"line":[57,123],"technology":[58],"reduce":[60,71],"communication":[61],"Compared":[63,135],"RC":[66],"wires,":[67,82],"lines":[69,110,179],"can":[70],"delay":[72],"by":[73,154,164],"up":[74],"factor":[77],"30":[79],"global":[81],"while":[83],"eliminating":[84],"need":[86],"repeaters.":[88],"However,":[89],"latency":[91],"reduction":[92,100],"comes":[93],"at":[94],"cost":[96],"comparable":[99],"in":[101,131],"bandwidth.":[102],"In":[103],"paper,":[105],"we":[106],"investigate":[107],"using":[108,176,187],"access":[112],"large":[113],"level-2":[114],"caches.":[116],"We":[117],"propose":[118],"family":[120],"cache":[124,141,152],"(TLC)":[125],"represent":[128],"different":[129],"points":[130],"latency/bandwidth":[133],"spectrum.":[134],"recently-proposed":[138],"dynamic":[139,161],"non-uniform":[140],"architecture":[142],"(DNUCA)":[143],"design,":[144],"base":[146],"TLC":[147,171,192,207],"design":[148,200],"reduces":[149,157],"required":[151],"area":[153],"18%":[155],"interconnection":[159],"network's":[160],"power":[162],"consumption":[163],"an":[165],"average":[166],"61%.":[168],"The":[169],"optimized":[170],"attain":[173],"similar":[174],"fewer":[177],"but":[180,215],"with":[181],"some":[182],"additional":[183],"complexity.":[184,221],"Simulation":[185],"results":[186],"full-system":[188],"simulation":[189],"show":[190],"provides":[193],"more":[194],"consistent":[195],"than":[197,212],"DNUCA":[199,213],"across":[201],"wide":[203],"variety":[204],"workloads.":[206],"caches":[208],"are":[209],"logically":[210],"simpler":[211],"designs,":[214],"require":[216],"greater":[217],"circuit":[218],"manufacturing":[220]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
