{"id":"https://openalex.org/W4249144718","doi":"https://doi.org/10.1109/micro.2003.1253181","title":"A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor","display_name":"A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W4249144718","doi":"https://doi.org/10.1109/micro.2003.1253181"},"language":"en","primary_location":{"id":"doi:10.1109/micro.2003.1253181","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.2003.1253181","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087813577","display_name":"S. Mukherjee","orcid":"https://orcid.org/0000-0002-2750-5071"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.S. Mukherjee","raw_affiliation_strings":["VSSAD, MMDC, Intel Corporation, Shrewsbury, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VSSAD, MMDC, Intel Corporation, Shrewsbury, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111955421","display_name":"Christopher Weaver","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Weaver","raw_affiliation_strings":["Advanced Computer Architecture Lab, EECS Department, University of Michigan, Ann Arbor, MI, USA","VSSAD, MMDC, Intel Corporation, Shrewsbury, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Computer Architecture Lab, EECS Department, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"VSSAD, MMDC, Intel Corporation, Shrewsbury, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024384625","display_name":"Joel Emer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Emer","raw_affiliation_strings":["VSSAD, MMDC, Intel Corporation, Shrewsbury, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VSSAD, MMDC, Intel Corporation, Shrewsbury, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108353805","display_name":"S.K. Reinhardt","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.K. Reinhardt","raw_affiliation_strings":["Advanced Computer Architecture Lab, EECS Department, University of Michigan, Ann Arbor, MI, USA","VSSAD, MMDC, Intel Corporation, Shrewsbury, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Computer Architecture Lab, EECS Department, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"VSSAD, MMDC, Intel Corporation, Shrewsbury, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112774619","display_name":"T. Austin","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Austin","raw_affiliation_strings":["Advanced Computer Architecture Lab, EECS Department, University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Computer Architecture Lab, EECS Department, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":28.8205,"has_fulltext":false,"cited_by_count":643,"citation_normalized_percentile":{"value":0.99850879,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"29","last_page":"40"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7893483638763428},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.6792678236961365},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6724463701248169},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.6312072277069092},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6280550360679626},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.606604278087616},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5766581296920776},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.49193382263183594},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.46089404821395874},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.4381641447544098},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.43413281440734863},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.42052337527275085},{"id":"https://openalex.org/keywords/vulnerability","display_name":"Vulnerability (computing)","score":0.4196883738040924},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.41012075543403625},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.38188636302948},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3732447028160095},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34712356328964233},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.23085373640060425},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.22443437576293945},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20893338322639465},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2026497721672058},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.15809640288352966},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12834802269935608},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09541058540344238},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08730265498161316}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7893483638763428},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.6792678236961365},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6724463701248169},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.6312072277069092},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6280550360679626},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.606604278087616},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5766581296920776},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.49193382263183594},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.46089404821395874},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.4381641447544098},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.43413281440734863},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.42052337527275085},{"id":"https://openalex.org/C95713431","wikidata":"https://www.wikidata.org/wiki/Q631425","display_name":"Vulnerability (computing)","level":2,"score":0.4196883738040924},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.41012075543403625},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.38188636302948},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3732447028160095},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34712356328964233},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.23085373640060425},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.22443437576293945},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20893338322639465},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2026497721672058},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.15809640288352966},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12834802269935608},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09541058540344238},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08730265498161316},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/micro.2003.1253181","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.2003.1253181","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W175437267","https://openalex.org/W1819167510","https://openalex.org/W1967835393","https://openalex.org/W2033346530","https://openalex.org/W2050431855","https://openalex.org/W2097117297","https://openalex.org/W2102863623","https://openalex.org/W2116097016","https://openalex.org/W2124536119","https://openalex.org/W2130653499","https://openalex.org/W2140351961","https://openalex.org/W2145064068","https://openalex.org/W2151345654","https://openalex.org/W2153456949","https://openalex.org/W2166474486","https://openalex.org/W2169213530","https://openalex.org/W3156377948","https://openalex.org/W4230988763","https://openalex.org/W4234365927","https://openalex.org/W4240029073","https://openalex.org/W4248445118","https://openalex.org/W4255653477","https://openalex.org/W6607184194","https://openalex.org/W6675837356","https://openalex.org/W6681059590","https://openalex.org/W6682541409"],"related_works":["https://openalex.org/W1916582918","https://openalex.org/W2044069930","https://openalex.org/W2622269177","https://openalex.org/W1523508240","https://openalex.org/W2381374827","https://openalex.org/W2102538861","https://openalex.org/W2109440006","https://openalex.org/W2122334461","https://openalex.org/W2165400042","https://openalex.org/W1553526993"],"abstract_inverted_index":{"Single-event":[0],"upsets":[1],"from":[2],"particle":[3],"strikes":[4],"have":[5],"become":[6],"a":[7,24,43,74,79,89,153,162],"key":[8,50],"challenge":[9],"in":[10,64,73,91,98,151],"microprocessor":[11],"design.":[12],"Techniques":[13],"to":[14,35,167,172],"deal":[15],"with":[16],"these":[17,47,173],"transients":[18],"faults":[19,59],"exist,":[20],"but":[21],"come":[22],"at":[23],"cost.":[25],"Designers":[26],"clearly":[27],"require":[28],"accurate":[29],"estimates":[30],"of":[31,52,108,126,183,199],"processor":[32,165],"error":[33,72,103,111],"rates":[34],"make":[36],"appropriate":[37],"cost/reliability":[38],"tradeoffs.":[39],"This":[40,179],"paper":[41],"describes":[42],"method":[44],"for":[45,187],"generating":[46,175],"estimates.":[48,178],"A":[49,101],"aspect":[51],"this":[53],"analysis":[54,180],"is":[55,105],"that":[56,88,92],"some":[57],"single-bit":[58],"(such":[60],"as":[61,85,113,130,143],"those":[62],"occurring":[63],"the":[65,86,106,121,131,188,200],"branch":[66],"predictor)":[67],"do":[68,95,155],"not":[69,96,156],"produce":[70],"an":[71,99],"program's":[75],"output.":[76],"We":[77,138,160],"define":[78],"structure's":[80,102],"architectural":[81],"vulnerability":[82],"factor":[83],"(AVF)":[84],"probability":[87],"fault":[90,154],"particular":[93],"structure":[94],"result":[97],"error.":[100],"rate":[104],"product":[107],"its":[109],"raw":[110],"rate,":[112],"determined":[114],"by":[115],"process":[116],"and":[117,120,148,185,191],"circuit":[118],"technology,":[119],"AVF.":[122],"Unfortunately,":[123],"computing":[124],"AVFs":[125,182],"complex":[127],"structures,":[128],"such":[129,142],"instruction":[132,189],"queue,":[133],"can":[134],"be":[135],"quite":[136],"involved.":[137],"identify":[139],"numerous":[140],"cases,":[141,174],"prefetches,":[144],"dynamically":[145],"dead":[146],"code,":[147],"wrong-path":[149],"instructions,":[150],"which":[152],"affect,":[157],"correct":[158],"execution.":[159],"instrument":[161],"detailed":[163],"1A64":[164],"simulator":[166],"map":[168],"bit-level":[169],"microarchitectural":[170],"state":[171],"per-structure":[176],"AVF":[177],"shows":[181],"28%":[184],"9%":[186],"queue":[190],"execution":[192],"units,":[193],"respectively,":[194],"averaged":[195],"across":[196],"dynamic":[197],"sections":[198],"entire":[201],"CPU2000":[202],"benchmark":[203],"suite.":[204]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":15},{"year":2024,"cited_by_count":19},{"year":2023,"cited_by_count":21},{"year":2022,"cited_by_count":23},{"year":2021,"cited_by_count":24},{"year":2020,"cited_by_count":26},{"year":2019,"cited_by_count":50},{"year":2018,"cited_by_count":30},{"year":2017,"cited_by_count":38},{"year":2016,"cited_by_count":39},{"year":2015,"cited_by_count":31},{"year":2014,"cited_by_count":33},{"year":2013,"cited_by_count":30},{"year":2012,"cited_by_count":44}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
