{"id":"https://openalex.org/W3041902045","doi":"https://doi.org/10.1109/metroind4.0iot48571.2020.9138256","title":"A New Class of Chaotic Sources in Programmable Logic Devices","display_name":"A New Class of Chaotic Sources in Programmable Logic Devices","publication_year":2020,"publication_date":"2020-06-01","ids":{"openalex":"https://openalex.org/W3041902045","doi":"https://doi.org/10.1109/metroind4.0iot48571.2020.9138256","mag":"3041902045"},"language":"en","primary_location":{"id":"doi:10.1109/metroind4.0iot48571.2020.9138256","is_oa":false,"landing_page_url":"https://doi.org/10.1109/metroind4.0iot48571.2020.9138256","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Workshop on Metrology for Industry 4.0 &amp; IoT","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008376177","display_name":"Tommaso Addabbo","orcid":"https://orcid.org/0000-0003-0168-9404"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Tommaso Addabbo","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011072460","display_name":"Ada Fort","orcid":"https://orcid.org/0000-0003-0916-1516"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Ada Fort","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064640550","display_name":"Riccardo Moretti","orcid":"https://orcid.org/0000-0002-1691-3846"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Riccardo Moretti","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076956231","display_name":"Marco Mugnaini","orcid":"https://orcid.org/0000-0002-2410-1581"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Mugnaini","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076041280","display_name":"Hadis Takaloo","orcid":"https://orcid.org/0000-0002-5457-0231"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Hadis Takaloo","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006110526","display_name":"Valerio Vignoli","orcid":"https://orcid.org/0000-0003-2509-6566"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Valerio Vignoli","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5008376177"],"corresponding_institution_ids":["https://openalex.org/I102064193"],"apc_list":null,"apc_paid":null,"fwci":0.2814,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.61478425,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"6","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10244","display_name":"Chaos control and synchronization","score":0.9760000109672546,"subfield":{"id":"https://openalex.org/subfields/3109","display_name":"Statistical and Nonlinear Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8009177446365356},{"id":"https://openalex.org/keywords/chaotic","display_name":"Chaotic","score":0.7715355157852173},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7614378333091736},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.7116377949714661},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7041589021682739},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5730671882629395},{"id":"https://openalex.org/keywords/entropy","display_name":"Entropy (arrow of time)","score":0.5501381754875183},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.5252969861030579},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.5205643773078918},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5112755298614502},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4910743236541748},{"id":"https://openalex.org/keywords/chaotic-systems","display_name":"Chaotic systems","score":0.4786573648452759},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.4647476077079773},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.41879788041114807},{"id":"https://openalex.org/keywords/chaos","display_name":"CHAOS (operating system)","score":0.417431503534317},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.40716007351875305},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3632144629955292},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34585338830947876},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2698611617088318},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1673021912574768},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.16009190678596497},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14661073684692383},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1333337128162384},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12167808413505554},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07336938381195068}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8009177446365356},{"id":"https://openalex.org/C2777052490","wikidata":"https://www.wikidata.org/wiki/Q5072826","display_name":"Chaotic","level":2,"score":0.7715355157852173},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7614378333091736},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.7116377949714661},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7041589021682739},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5730671882629395},{"id":"https://openalex.org/C106301342","wikidata":"https://www.wikidata.org/wiki/Q4117933","display_name":"Entropy (arrow of time)","level":2,"score":0.5501381754875183},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.5252969861030579},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.5205643773078918},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5112755298614502},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4910743236541748},{"id":"https://openalex.org/C2987469083","wikidata":"https://www.wikidata.org/wiki/Q166314","display_name":"Chaotic systems","level":3,"score":0.4786573648452759},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.4647476077079773},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.41879788041114807},{"id":"https://openalex.org/C2779374083","wikidata":"https://www.wikidata.org/wiki/Q5011038","display_name":"CHAOS (operating system)","level":2,"score":0.417431503534317},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.40716007351875305},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3632144629955292},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34585338830947876},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2698611617088318},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1673021912574768},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.16009190678596497},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14661073684692383},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1333337128162384},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12167808413505554},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07336938381195068},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/metroind4.0iot48571.2020.9138256","is_oa":false,"landing_page_url":"https://doi.org/10.1109/metroind4.0iot48571.2020.9138256","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Workshop on Metrology for Industry 4.0 &amp; IoT","raw_type":"proceedings-article"},{"id":"pmh:oai:usiena-air.unisi.it:11365/1123119","is_oa":false,"landing_page_url":"http://hdl.handle.net/11365/1123119","pdf_url":null,"source":{"id":"https://openalex.org/S4377196319","display_name":"Use Siena air (University of Siena)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I102064193","host_organization_name":"University of Siena","host_organization_lineage":["https://openalex.org/I102064193"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1511378164","https://openalex.org/W1588877666","https://openalex.org/W1986590348","https://openalex.org/W2009349379","https://openalex.org/W2030022595","https://openalex.org/W2067235573","https://openalex.org/W2117205818","https://openalex.org/W2157652868","https://openalex.org/W2161890359","https://openalex.org/W2167352984","https://openalex.org/W2293871667","https://openalex.org/W2538926017","https://openalex.org/W2792898086","https://openalex.org/W2799438285","https://openalex.org/W2907552407","https://openalex.org/W2942596950","https://openalex.org/W2947486590","https://openalex.org/W2954169045","https://openalex.org/W2966347221","https://openalex.org/W2966695223","https://openalex.org/W2971859984","https://openalex.org/W3012270870","https://openalex.org/W3140517496","https://openalex.org/W4249971531","https://openalex.org/W6630548010","https://openalex.org/W6763096076","https://openalex.org/W6764377991"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W2060295827","https://openalex.org/W3105918491","https://openalex.org/W2462231960","https://openalex.org/W2596493166","https://openalex.org/W2359463936","https://openalex.org/W2124423430","https://openalex.org/W1569147302","https://openalex.org/W2381638859","https://openalex.org/W2124848588"],"abstract_inverted_index":{"We":[0],"introduce":[1],"a":[2,19,39,55],"new":[3],"method":[4],"for":[5],"the":[6],"design":[7],"of":[8,22],"information":[9],"entropy":[10,42],"sources":[11],"in":[12,47],"Programmable":[13],"Logic":[14],"Devices":[15],"(PLDs),":[16],"based":[17],"on":[18,54],"novel":[20],"class":[21],"circuits":[23],"called":[24],"Digital":[25],"Nonlinear":[26],"Oscillators":[27],"(DNOs)":[28],"supporting":[29],"complex":[30],"dynamics,":[31],"including":[32],"chaos.":[33],"Following":[34],"this":[35],"method,":[36],"we":[37],"designed":[38],"fully":[40],"digital":[41],"source,":[43],"i.e.":[44],"entirely":[45],"described":[46],"VHDL.":[48],"The":[49],"solution":[50],"has":[51],"been":[52],"implemented":[53],"Xilinx":[56],"FPGA,":[57],"showing,":[58],"according":[59],"to":[60],"some":[61],"tuning,":[62],"periodic":[63],"and":[64],"chaotic":[65],"behaviors.":[66]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2022,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2020-07-16T00:00:00"}
