{"id":"https://openalex.org/W4310174468","doi":"https://doi.org/10.1109/memocode57689.2022.9954598","title":"Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs","display_name":"Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs","publication_year":2022,"publication_date":"2022-10-13","ids":{"openalex":"https://openalex.org/W4310174468","doi":"https://doi.org/10.1109/memocode57689.2022.9954598"},"language":"en","primary_location":{"id":"doi:10.1109/memocode57689.2022.9954598","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memocode57689.2022.9954598","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002090945","display_name":"Samira Ait Bensaid","orcid":null},"institutions":[{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I4210085861","display_name":"Laboratoire d'Int\u00e9gration des Syst\u00e8mes et des Technologies","ror":"https://ror.org/000dbcc61","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I277688954","https://openalex.org/I4210085861","https://openalex.org/I4210117989"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Samira Ait Bensaid","raw_affiliation_strings":["Université Paris-Saclay, CEA, List,Palaiseau,France,F-91120","Laboratoire Environnement de Conception & Architecture"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Université Paris-Saclay, CEA, List,Palaiseau,France,F-91120","institution_ids":["https://openalex.org/I4210085861","https://openalex.org/I2738703131"]},{"raw_affiliation_string":"Laboratoire Environnement de Conception & Architecture","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112332461","display_name":"Mihail As\u0103voae","orcid":null},"institutions":[{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I4210085861","display_name":"Laboratoire d'Int\u00e9gration des Syst\u00e8mes et des Technologies","ror":"https://ror.org/000dbcc61","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I277688954","https://openalex.org/I4210085861","https://openalex.org/I4210117989"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Mihail Asavoae","raw_affiliation_strings":["Université Paris-Saclay, CEA, List,Palaiseau,France,F-91120","Laboratoire Environnement de Conception & Architecture"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Université Paris-Saclay, CEA, List,Palaiseau,France,F-91120","institution_ids":["https://openalex.org/I4210085861","https://openalex.org/I2738703131"]},{"raw_affiliation_string":"Laboratoire Environnement de Conception & Architecture","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021318654","display_name":"Farhat Thabet","orcid":null},"institutions":[{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I4210085861","display_name":"Laboratoire d'Int\u00e9gration des Syst\u00e8mes et des Technologies","ror":"https://ror.org/000dbcc61","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I277688954","https://openalex.org/I4210085861","https://openalex.org/I4210117989"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Farhat Thabet","raw_affiliation_strings":["Université Paris-Saclay, CEA, List,Palaiseau,France,F-91120","Laboratoire Environnement de Conception & Architecture"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Université Paris-Saclay, CEA, List,Palaiseau,France,F-91120","institution_ids":["https://openalex.org/I4210085861","https://openalex.org/I2738703131"]},{"raw_affiliation_string":"Laboratoire Environnement de Conception & Architecture","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078263499","display_name":"Mathieu Jan","orcid":"https://orcid.org/0000-0002-3016-8109"},"institutions":[{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I4210085861","display_name":"Laboratoire d'Int\u00e9gration des Syst\u00e8mes et des Technologies","ror":"https://ror.org/000dbcc61","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I277688954","https://openalex.org/I4210085861","https://openalex.org/I4210117989"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Mathieu Jan","raw_affiliation_strings":["Université Paris-Saclay, CEA, List,Palaiseau,France,F-91120","Laboratoire Environnement de Conception & Architecture"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Université Paris-Saclay, CEA, List,Palaiseau,France,F-91120","institution_ids":["https://openalex.org/I4210085861","https://openalex.org/I2738703131"]},{"raw_affiliation_string":"Laboratoire Environnement de Conception & Architecture","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"57","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9137970209121704},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8297734260559082},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7830522060394287},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6433525085449219},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.6044727563858032},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5931154489517212},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5611048936843872},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5597723722457886},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.5424514412879944},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.5385884046554565},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5233551859855652},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46679455041885376},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.46212196350097656},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.46169766783714294},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4315764904022217},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4261641800403595},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3194236159324646},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2990548312664032}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9137970209121704},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8297734260559082},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7830522060394287},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6433525085449219},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.6044727563858032},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5931154489517212},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5611048936843872},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5597723722457886},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.5424514412879944},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.5385884046554565},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5233551859855652},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46679455041885376},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.46212196350097656},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.46169766783714294},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4315764904022217},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4261641800403595},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3194236159324646},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2990548312664032},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/memocode57689.2022.9954598","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memocode57689.2022.9954598","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-04440573v1","is_oa":false,"landing_page_url":"https://hal.science/hal-04440573","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:HAL:hal-04477112v1","is_oa":false,"landing_page_url":"https://hal.science/hal-04477112","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), Oct 2022, Shanghai, China. pp.1-8, ⟨10.1109/MEMOCODE57689.2022.9954598⟩","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1482275438","https://openalex.org/W1502103334","https://openalex.org/W1566056797","https://openalex.org/W1983394510","https://openalex.org/W2012471639","https://openalex.org/W2020291837","https://openalex.org/W2032094184","https://openalex.org/W2122666034","https://openalex.org/W2133088975","https://openalex.org/W2152630897","https://openalex.org/W2163529295","https://openalex.org/W2189263796","https://openalex.org/W2415551696","https://openalex.org/W2511362782","https://openalex.org/W2562688732","https://openalex.org/W2725094902","https://openalex.org/W2964898699","https://openalex.org/W3007624024","https://openalex.org/W3033074846","https://openalex.org/W3046283850","https://openalex.org/W4240172596","https://openalex.org/W4283725487","https://openalex.org/W4298395725","https://openalex.org/W6682577152","https://openalex.org/W6725655191","https://openalex.org/W6740348905","https://openalex.org/W6772606762"],"related_works":["https://openalex.org/W4400188904","https://openalex.org/W4247613350","https://openalex.org/W2019183874","https://openalex.org/W2004059337","https://openalex.org/W2104167653","https://openalex.org/W1994289828","https://openalex.org/W1588764976","https://openalex.org/W2510306697","https://openalex.org/W2146897337","https://openalex.org/W4312333632"],"abstract_inverted_index":{"Static":[0],"worst-case":[1,34,90],"timing":[2,25,35,91],"analysis":[3,36],"is":[4,14,37],"important":[5],"in":[6,47,68,111],"the":[7,23,33,82,101,120],"context":[8],"of":[9,103],"safety-critical":[10],"systems":[11],"as":[12],"it":[13],"one":[15],"approach":[16,99],"that":[17],"could":[18],"be":[19],"used":[20],"to":[21,29,84],"validate":[22],"required":[24,51],"bounds.":[26],"In":[27,93],"order":[28],"derive":[30],"accurate":[31],"bounds,":[32],"performed":[38],"under":[39],"(micro)-architecture":[40,52,87],"consideration,":[41],"consequently,":[42],"these":[43],"bounds":[44],"are":[45,54],"expressed":[46],"processor":[48,60,108],"cycles.":[49],"The":[50],"models":[53,88,106],"usually":[55],"constructed":[56],"by":[57],"hand,":[58],"from":[59,107],"manuals":[61],"and":[62,75],"validated":[63],"through":[64],"testing.":[65],"Recent":[66],"advances":[67],"hardware":[69,73],"design":[70],"promote":[71],"open":[72],"initiatives":[74],"high-level":[76,112],"Hardware":[77,122],"Description":[78],"Languages":[79],"(HDLs),":[80],"revisiting":[81],"perspectives":[83],"automatically":[85],"construct":[86],"for":[89],"analysis.":[92],"this":[94],"paper,":[95],"we":[96,126],"present":[97],"an":[98],"concerning":[100],"construction":[102],"pipeline":[104],"datapath":[105],"designs":[109],"described":[110],"HDLs.":[113],"We":[114],"propose":[115],"a":[116],"methodology":[117],"based":[118],"on":[119,128],"Chisel/FIRRTL":[121],"Compiler":[123],"Framework":[124],"which":[125],"apply":[127],"several":[129],"open-source":[130],"RISC-V":[131],"processors.":[132]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}