{"id":"https://openalex.org/W2566529786","doi":"https://doi.org/10.1109/memcod.2016.7797754","title":"Accelerating schedule space exploration of multi-threaded programs with GPUs","display_name":"Accelerating schedule space exploration of multi-threaded programs with GPUs","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W2566529786","doi":"https://doi.org/10.1109/memcod.2016.7797754","mag":"2566529786"},"language":"en","primary_location":{"id":"doi:10.1109/memcod.2016.7797754","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2016.7797754","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000621226","display_name":"Prakhar Banga","orcid":null},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Prakhar Banga","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur, India","institution_ids":["https://openalex.org/I94234084"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006146375","display_name":"Atul Pai","orcid":null},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Atul Pai","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur, India","institution_ids":["https://openalex.org/I94234084"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014601092","display_name":"Subhajit Roy","orcid":"https://orcid.org/0000-0002-3394-023X"},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Subhajit Roy","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur, India","institution_ids":["https://openalex.org/I94234084"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071818120","display_name":"Mainak Chaudhuri","orcid":"https://orcid.org/0000-0001-8185-1082"},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mainak Chaudhuri","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur, India","institution_ids":["https://openalex.org/I94234084"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5000621226"],"corresponding_institution_ids":["https://openalex.org/I94234084"],"apc_list":null,"apc_paid":null,"fwci":0.3233,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61129312,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"115","last_page":"124"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12127","display_name":"Software System Performance and Reliability","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8882712721824646},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.8281539678573608},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.6646089553833008},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6195731163024902},{"id":"https://openalex.org/keywords/posix-threads","display_name":"POSIX Threads","score":0.6017279624938965},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.5668234825134277},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.49470970034599304},{"id":"https://openalex.org/keywords/transactional-memory","display_name":"Transactional memory","score":0.4320257306098938},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.4195685386657715},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4176673889160156},{"id":"https://openalex.org/keywords/context-switch","display_name":"Context switch","score":0.41223156452178955},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.322867214679718},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3105161190032959},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.30681803822517395},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2820221781730652}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8882712721824646},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.8281539678573608},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.6646089553833008},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6195731163024902},{"id":"https://openalex.org/C41138395","wikidata":"https://www.wikidata.org/wiki/Q928112","display_name":"POSIX Threads","level":3,"score":0.6017279624938965},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.5668234825134277},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.49470970034599304},{"id":"https://openalex.org/C134277064","wikidata":"https://www.wikidata.org/wiki/Q878206","display_name":"Transactional memory","level":3,"score":0.4320257306098938},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.4195685386657715},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4176673889160156},{"id":"https://openalex.org/C53833338","wikidata":"https://www.wikidata.org/wiki/Q1061424","display_name":"Context switch","level":2,"score":0.41223156452178955},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.322867214679718},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3105161190032959},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.30681803822517395},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2820221781730652},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/memcod.2016.7797754","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2016.7797754","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1493367105","https://openalex.org/W1868584616","https://openalex.org/W2087074916","https://openalex.org/W2104644701","https://openalex.org/W2110852599","https://openalex.org/W2111413199","https://openalex.org/W2112117314","https://openalex.org/W2119494620","https://openalex.org/W2120027538","https://openalex.org/W2134633067","https://openalex.org/W2135395375","https://openalex.org/W2135948849","https://openalex.org/W2142573689","https://openalex.org/W2148011508","https://openalex.org/W2158124716","https://openalex.org/W2169875292","https://openalex.org/W2398358240","https://openalex.org/W4230480080","https://openalex.org/W4239813889","https://openalex.org/W4254906220"],"related_works":["https://openalex.org/W2104688710","https://openalex.org/W3130341238","https://openalex.org/W2215749729","https://openalex.org/W1520933080","https://openalex.org/W2742081515","https://openalex.org/W2748693150","https://openalex.org/W2369684220","https://openalex.org/W3129116740","https://openalex.org/W2152163809","https://openalex.org/W2135868636"],"abstract_inverted_index":{"Given":[0],"an":[1,156,278],"input":[2,152,168],"that":[3,101,145],"can":[4,19,208],"trigger":[5],"a":[6,10,23,60,69,98,195,239,271],"concurrency":[7,245,259],"bug,":[8],"only":[9],"subset":[11],"of":[12,32,63,82,115,150,166,204,216,235,257],"possible":[13],"thread":[14,33,161,222],"schedules":[15,34,64,183],"satisfying":[16],"certain":[17],"constraints":[18],"actually":[20],"cause":[21],"such":[22],"bug":[24,39,53],"to":[25,50,65,76,109,129,191,213,224,263],"manifest.":[26],"Recent":[27],"proposals":[28],"on":[29,38,155,184,198,270,277],"controlled":[30],"randomization":[31],"with":[35,94],"concrete":[36],"guarantees":[37],"detection":[40,54],"probabilities":[41],"have":[42],"opened":[43],"promising":[44],"avenues":[45],"in":[46,73],"this":[47,87,229],"direction.":[48],"However,":[49],"boost":[51],"the":[52,78,83,103,147,151,167,175,182,185,202,205,252,264,298,301],"probability,":[55],"these":[56],"techniques":[57],"typically":[58,162],"require":[59],"significant":[61],"number":[62],"be":[66,209],"explored.":[67],"As":[68],"result,":[70],"it":[71,188],"is,":[72],"general,":[74],"beneficial":[75],"accelerate":[77,111],"schedule":[79,112,148,165,176,197,287],"space":[80,113,149,177,288],"exploration":[81,289],"multi-threaded":[84,117,125,153,292],"programs.":[85,118],"In":[86,228],"paper,":[88,230],"we":[89,231],"introduce":[90],"Simultaneous":[91],"Interleaving":[92],"Exploration":[93],"Controlled":[95],"Sequencing":[96],"(SINECOSEQ),":[97],"generic":[99],"framework":[100,121,172],"leverages":[102],"high-performance":[104],"graphics":[105],"processing":[106],"units":[107],"(GPUs)":[108],"significantly":[110,284],"navigation":[114],"general-purpose":[116],"The":[119,170],"SINE":[120],"accepts":[122],"POSIX":[123],"compliant":[124,143],"programs,":[126],"instruments":[127],"them":[128],"intercept":[130],"all":[131],"shared":[132],"memory":[133],"accesses,":[134],"and":[135,193,294,300],"automatically":[136],"generates":[137],"CUDA":[138],"(Compute":[139],"Unified":[140],"Device":[141],"Architecture)":[142],"code":[144],"navigates":[146],"program":[154],"NVIDIA":[157,279],"GPU.":[158],"Each":[159],"GPU":[160,200,221,282],"explores":[163],"one":[164,233],"program.":[169],"COSEQ":[171],"decides":[173],"how":[174],"is":[178,189,249],"navigated":[179],"by":[180,219,237,251],"architecting":[181],"fly.":[186],"While":[187],"straightforward":[190],"construct":[192],"navigate":[194],"different":[196],"each":[199,220],"thread,":[201],"performance":[203],"resulting":[206],"technique":[207],"very":[210],"poor":[211],"due":[212],"disparate":[214],"pieces":[215],"codes":[217],"executed":[218],"leading":[223],"full":[225],"control":[226],"divergence.":[227],"demonstrate":[232],"application":[234],"SINECOSEQ":[236],"proposing":[238],"new":[240],"GPU-friendly":[241],"scheduler":[242,256],"for":[243,290],"accelerated":[244],"testing":[246,260],"(ACT),":[247],"which":[248],"inspired":[250],"recently":[253],"proposed":[254],"randomized":[255],"probabilistic":[258],"(PCT).":[261],"Compared":[262],"state-of-the-art":[265],"parallel":[266],"PCT":[267],"(PPCT)":[268],"implementation":[269],"twelve-core":[272],"CPU,":[273],"our":[274],"proposal":[275],"implemented":[276],"Kepler":[280],"K20c":[281],"card":[283],"speeds":[285],"up":[286],"eight":[291],"applications":[293],"kernels":[295],"drawn":[296],"from":[297],"Phoenix":[299],"PARSEC":[302],"suites.":[303]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}