{"id":"https://openalex.org/W2182130297","doi":"https://doi.org/10.1109/memcod.2015.7340484","title":"Reducing power with activity trigger analysis","display_name":"Reducing power with activity trigger analysis","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W2182130297","doi":"https://doi.org/10.1109/memcod.2015.7340484","mag":"2182130297"},"language":"en","primary_location":{"id":"doi:10.1109/memcod.2015.7340484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2015.7340484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071009619","display_name":"Jan L\u00e1n\u00edk","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156361","display_name":"Verimag","ror":"https://ror.org/05afmzm11","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210156361","https://openalex.org/I4210159245","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Jan Lanik","raw_affiliation_strings":["Verimag"],"affiliations":[{"raw_affiliation_string":"Verimag","institution_ids":["https://openalex.org/I4210156361"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091278491","display_name":"Julien Legriel","orcid":"https://orcid.org/0009-0003-6183-6004"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Julien Legriel","raw_affiliation_strings":["Afrenta"],"affiliations":[{"raw_affiliation_string":"Afrenta","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003499945","display_name":"Erwan Piriou","orcid":null},"institutions":[{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I4210085861","display_name":"Laboratoire d'Int\u00e9gration des Syst\u00e8mes et des Technologies","ror":"https://ror.org/000dbcc61","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I277688954","https://openalex.org/I4210085861","https://openalex.org/I4210117989"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Erwan Piriou","raw_affiliation_strings":["CEA-LIST"],"affiliations":[{"raw_affiliation_string":"CEA-LIST","institution_ids":["https://openalex.org/I4210085861","https://openalex.org/I2738703131"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030968202","display_name":"E. Viaud","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Emmanuel Viaud","raw_affiliation_strings":["Afrenta"],"affiliations":[{"raw_affiliation_string":"Afrenta","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007596573","display_name":"Fahim Rahim","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Fahim Rahim","raw_affiliation_strings":["Afrenta"],"affiliations":[{"raw_affiliation_string":"Afrenta","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012209374","display_name":"Oded Maler","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156361","display_name":"Verimag","ror":"https://ror.org/05afmzm11","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210156361","https://openalex.org/I4210159245","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Oded Maler","raw_affiliation_strings":["Verimag"],"affiliations":[{"raw_affiliation_string":"Verimag","institution_ids":["https://openalex.org/I4210156361"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083563575","display_name":"Solaiman Rahim","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Solaiman Rahim","raw_affiliation_strings":["Afrenta"],"affiliations":[{"raw_affiliation_string":"Afrenta","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5071009619"],"corresponding_institution_ids":["https://openalex.org/I4210156361"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.096062,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"169","last_page":"178"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.8548568487167358},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.799201250076294},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7473034262657166},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.591897189617157},{"id":"https://openalex.org/keywords/closing","display_name":"Closing (real estate)","score":0.5613216757774353},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.5465091466903687},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.5130216479301453},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.484923392534256},{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.4766688644886017},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4614412188529968},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4315783381462097},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4261144995689392},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4081459045410156},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38665083050727844},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3817744851112366},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.21688997745513916},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18852025270462036},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.18056342005729675},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.17803320288658142},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15297776460647583},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14485254883766174},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13964617252349854},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0869835913181305}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.8548568487167358},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.799201250076294},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7473034262657166},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.591897189617157},{"id":"https://openalex.org/C2778775528","wikidata":"https://www.wikidata.org/wiki/Q5135432","display_name":"Closing (real estate)","level":2,"score":0.5613216757774353},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.5465091466903687},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.5130216479301453},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.484923392534256},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.4766688644886017},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4614412188529968},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4315783381462097},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4261144995689392},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4081459045410156},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38665083050727844},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3817744851112366},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.21688997745513916},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18852025270462036},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.18056342005729675},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.17803320288658142},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15297776460647583},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14485254883766174},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13964617252349854},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0869835913181305},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/memcod.2015.7340484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2015.7340484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:cea-01836860v1","is_oa":false,"landing_page_url":"https://cea.hal.science/cea-01836860","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), Sep 2015, Austin, United States. pp.169-178, &#x27E8;10.1109/MEMCOD.2015.7340484&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.699999988079071,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1491593738","https://openalex.org/W1522951882","https://openalex.org/W1528837436","https://openalex.org/W1540180001","https://openalex.org/W1549166962","https://openalex.org/W1554331564","https://openalex.org/W1633471522","https://openalex.org/W1787074469","https://openalex.org/W1976346464","https://openalex.org/W1996445094","https://openalex.org/W2077628429","https://openalex.org/W2082321038","https://openalex.org/W2097136089","https://openalex.org/W2098560306","https://openalex.org/W2115283580","https://openalex.org/W2118214977","https://openalex.org/W2118791871","https://openalex.org/W2124364098","https://openalex.org/W2137564865","https://openalex.org/W2152849223","https://openalex.org/W2154550022","https://openalex.org/W2164050549","https://openalex.org/W2166243422","https://openalex.org/W3106729728","https://openalex.org/W3138459719","https://openalex.org/W3143918848","https://openalex.org/W4234129059","https://openalex.org/W6669866391","https://openalex.org/W6674969274","https://openalex.org/W6677926612"],"related_works":["https://openalex.org/W2061180121","https://openalex.org/W2259094912","https://openalex.org/W2546524276","https://openalex.org/W2152979262","https://openalex.org/W4226239708","https://openalex.org/W2005728592","https://openalex.org/W3127845477","https://openalex.org/W2113774150","https://openalex.org/W229101532","https://openalex.org/W2188626039"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"propose":[4],"and":[5,22,40,48,62],"implement":[6],"a":[7,30,42,83,95],"methodology":[8],"for":[9,44,99],"power":[10,85,93],"reduction":[11,86],"in":[12],"digital":[13],"circuits,":[14],"closing":[15],"the":[16,70],"gap":[17],"between":[18],"conceptual":[19],"(by":[20,24],"designer)":[21],"local":[23,36],"EDA)":[25],"clock":[26,37],"gating.":[27],"We":[28,81],"introduce":[29],"new":[31],"class":[32],"of":[33,55,65,91],"coarse":[34],"grained":[35],"gating":[38],"conditions":[39,47,57],"develop":[41],"method":[43],"detecting":[45],"such":[46],"formally":[49],"proving":[50],"their":[51],"correctness.":[52],"The":[53],"detection":[54],"these":[56],"relies":[58],"on":[59,76,94],"architecture":[60],"characterization":[61],"statistical":[63],"analysis":[64],"simulation,":[66],"all":[67],"done":[68],"at":[69],"RTL.":[71],"Formal":[72],"verification":[73],"is":[74],"performed":[75],"an":[77],"abstract":[78],"circuit":[79,97],"model.":[80],"demonstrate":[82],"significant":[84],"from":[87],"33":[88],"to":[89],"40%":[90],"total":[92],"clusterized":[96],"design":[98],"video":[100],"processing.":[101]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-02-27T16:54:17.756197","created_date":"2025-10-10T00:00:00"}
