{"id":"https://openalex.org/W3146332461","doi":"https://doi.org/10.1109/memcod.2009.5185385","title":"Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation","display_name":"Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation","publication_year":2009,"publication_date":"2009-07-01","ids":{"openalex":"https://openalex.org/W3146332461","doi":"https://doi.org/10.1109/memcod.2009.5185385","mag":"3146332461"},"language":"en","primary_location":{"id":"doi:10.1109/memcod.2009.5185385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2009.5185385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064639991","display_name":"Eric S. Chung","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric S. Chung","raw_affiliation_strings":["Computer Architecture Laboratory at Carnegie Mellon, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture Laboratory at Carnegie Mellon, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019376179","display_name":"James C. Hoe","orcid":"https://orcid.org/0000-0002-9302-5287"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James C. Hoe","raw_affiliation_strings":["Computer Architecture Laboratory at Carnegie Mellon, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture Laboratory at Carnegie Mellon, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"40","issue":null,"first_page":"98","last_page":"107"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8633745312690735},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7168628573417664},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6735419034957886},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.66081303358078},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6172317266464233},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5240476131439209},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5030156970024109},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.45397165417671204},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.45250213146209717},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.435403972864151},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4156429171562195},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.1916186809539795}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8633745312690735},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7168628573417664},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6735419034957886},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.66081303358078},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6172317266464233},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5240476131439209},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5030156970024109},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.45397165417671204},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.45250213146209717},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.435403972864151},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4156429171562195},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.1916186809539795},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/memcod.2009.5185385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2009.5185385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320330412","display_name":"Scheme for Promotion of Academic and Research Collaboration","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W65216360","https://openalex.org/W1498455513","https://openalex.org/W1978507093","https://openalex.org/W1986314250","https://openalex.org/W1989016096","https://openalex.org/W2098681688","https://openalex.org/W2120635877","https://openalex.org/W2161115325","https://openalex.org/W4244878519","https://openalex.org/W4246596690"],"related_works":["https://openalex.org/W1940589050","https://openalex.org/W2355721938","https://openalex.org/W2387608311","https://openalex.org/W2973764441","https://openalex.org/W2086248387","https://openalex.org/W2350798290","https://openalex.org/W39373273","https://openalex.org/W1542759904","https://openalex.org/W2388465587","https://openalex.org/W1149367995"],"abstract_inverted_index":{"We":[0,145],"have":[1],"developed":[2],"a":[3,23,30,40,58,76,80,104],"16-way":[4],"multithreaded":[5,138],"microprocessor":[6,45],"called":[7],"BlueSPARC.":[8],"This":[9,66],"in-order,":[10],"high-throughput":[11],"processor":[12],"incorporates":[13],"complex":[14],"features":[15],"such":[16],"as":[17],"privileged":[18],"operations,":[19],"memory":[20],"management,":[21],"and":[22,79,113,149,160],"non-blocking":[24],"cache":[25],"subsystem.":[26],"When":[27],"supported":[28],"by":[29],"hybrid":[31],"simulation":[32],"technique":[33],"that":[34,108],"handles":[35],"rare,":[36],"unimplemented":[37],"behaviors":[38],"in":[39,71,95,154],"software":[41],"host,":[42],"the":[43,85,89,97,117,121,125,133,142,147,155],"BlueSPARC":[44,143],"runs":[46],"unmodified":[47],"UltraSPARC":[48],"III-based":[49],"commercial":[50],"applications":[51],"on":[52,57,141],"Solaris":[53],"8":[54],"while":[55],"hosted":[56],"single":[59],"Xilinx":[60],"XCV2P70":[61],"FPGA":[62],"clocked":[63],"at":[64],"90MHz.":[65],"significant":[67],"effort":[68],"was":[69],"achieved":[70],"under":[72],"one":[73],"man-year":[74],"using":[75],"high-level":[77,81],"language":[78,101],"validation":[82,127,153],"approach.":[83],"In":[84,116],"first":[86],"part":[87,119],"of":[88,120,136,157],"paper,":[90,122],"we":[91,123,129],"describe":[92],"our":[93,150],"experience":[94],"applying":[96],"Bluespec":[98],"SystemVerilog":[99],"(BSV)":[100],"to":[102,131,152],"develop":[103],"large":[105],"hardware":[106],"design":[107],"must":[109],"meet":[110],"specific":[111],"area":[112],"performance":[114],"requirements.":[115],"second":[118],"present":[124],"FPGA-accelerated":[126],"approach":[128],"employed":[130],"check":[132],"correct":[134],"execution":[135],"real":[137],"programs":[139],"running":[140],"processor.":[144],"discuss":[146],"challenges":[148],"solutions":[151],"presence":[156],"full-system":[158],"interactions":[159],"microarchitectural":[161],"nondeterminism.":[162]},"counts_by_year":[{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
