{"id":"https://openalex.org/W2114398825","doi":"https://doi.org/10.1109/memcod.2006.1695900","title":"Low-power hardware synthesis from TRS-based specifications","display_name":"Low-power hardware synthesis from TRS-based specifications","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2114398825","doi":"https://doi.org/10.1109/memcod.2006.1695900","mag":"2114398825"},"language":"en","primary_location":{"id":"doi:10.1109/memcod.2006.1695900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2006.1695900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066646559","display_name":"Gaurav Singh","orcid":"https://orcid.org/0000-0002-8418-0154"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Singh","raw_affiliation_strings":["FERMAT Laboratory, Electrical and Computer Engineering, Virginia Technology, Blacksburg, VA, USA","FERMAT Lab, Virginia Tech, Blacksburg, VA, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"FERMAT Laboratory, Electrical and Computer Engineering, Virginia Technology, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"FERMAT Lab, Virginia Tech, Blacksburg, VA, USA#TAB#","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021517996","display_name":"Sandeep K. Shukla","orcid":"https://orcid.org/0000-0001-5525-7426"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.K. Shukla","raw_affiliation_strings":["FERMAT Laboratory, Electrical and Computer Engineering, Virginia Technology, Blacksburg, VA, USA","FERMAT Lab, Virginia Tech, Blacksburg, VA, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"FERMAT Laboratory, Electrical and Computer Engineering, Virginia Technology, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"FERMAT Lab, Virginia Tech, Blacksburg, VA, USA#TAB#","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":0.4464,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.54683451,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"47","issue":null,"first_page":"49","last_page":"58"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8343560695648193},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6538971662521362},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6337800025939941},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.630237877368927},{"id":"https://openalex.org/keywords/rewriting","display_name":"Rewriting","score":0.590226411819458},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5034260153770447},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.4296445846557617},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42323336005210876},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4219490885734558},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.41552406549453735},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39406639337539673},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3513326048851013},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.23709985613822937}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8343560695648193},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6538971662521362},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6337800025939941},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.630237877368927},{"id":"https://openalex.org/C154690210","wikidata":"https://www.wikidata.org/wiki/Q1668499","display_name":"Rewriting","level":2,"score":0.590226411819458},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5034260153770447},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.4296445846557617},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42323336005210876},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4219490885734558},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.41552406549453735},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39406639337539673},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3513326048851013},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.23709985613822937},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/memcod.2006.1695900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2006.1695900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W162006361","https://openalex.org/W1577039630","https://openalex.org/W1583295953","https://openalex.org/W1683919907","https://openalex.org/W1684368954","https://openalex.org/W2051253101","https://openalex.org/W2065260591","https://openalex.org/W2070316659","https://openalex.org/W2092360141","https://openalex.org/W2124080028","https://openalex.org/W2145843790","https://openalex.org/W2156848920","https://openalex.org/W2158615334","https://openalex.org/W2162705565","https://openalex.org/W2165867688","https://openalex.org/W4230919050","https://openalex.org/W4239807970","https://openalex.org/W4242933366","https://openalex.org/W4251532145","https://openalex.org/W4252038519","https://openalex.org/W6637127530"],"related_works":["https://openalex.org/W2269990635","https://openalex.org/W2543290882","https://openalex.org/W3013057549","https://openalex.org/W1980040075","https://openalex.org/W1490270176","https://openalex.org/W1604320855","https://openalex.org/W2029518208","https://openalex.org/W2295153704","https://openalex.org/W282396022","https://openalex.org/W2159022270"],"abstract_inverted_index":{"Synthesis":[0],"from":[1,80,90,116,217],"guarded":[2,75],"atomic":[3,76,227],"actions":[4,131,147,171,228,247],"used":[5],"for":[6,20,36,248],"high-level":[7],"descriptions":[8],"of":[9,45,61,68,94,130,139,145,151,157,199,208,225,245],"hardware":[10,37,153],"designs":[11,23,154,215],"has":[12],"been":[13],"shown":[14],"to":[15,135,180,196,229],"be":[16],"a":[17,69,178,193,231],"successful":[18],"methodology":[19,29],"generating":[21],"efficient":[22],"(Arvind":[24],"et":[25,103,110],"al.,":[26,111],"2004).":[27],"This":[28],"uses":[30,222],"CAOS":[31,62,117,194],"(concurrent":[32],"action":[33],"oriented":[34],"specifications)":[35],"description":[38],"which":[39],"is":[40,63,71,88,177],"based":[41],"on":[42],"the":[43,66,91,120,124,137,140,146,149,152,158,185,206,223,226,235,238,243,246],"idea":[44],"term":[46],"rewriting":[47],"systems":[48],"(TRS's)":[49],"(Baader":[50],"and":[51,55,106,126,201,211],"Nipkov,":[52],"1998;":[53],"Hoe":[54],"Arvind,":[56],"1999).":[57],"A":[58],"prime":[59],"example":[60],"Bluespec":[64],"where":[65],"behavior":[67],"design":[70],"described":[72],"using":[73,97],"various":[74],"actions.":[77],"Hardware":[78,113],"synthesis":[79,96],"such":[81,170,218],"specifications":[82],"can":[83,118],"infer":[84],"more":[85],"parallelism":[86,121],"than":[87],"possible":[89],"traditional":[92],"methods":[93],"behavioral":[95],"CDFGs":[98],"(control":[99],"data-flow":[100],"graphs)":[101],"(Gupta":[102],"al.;":[104],"Chang":[105],"Pedram,":[107],"1999;":[108],"Lakshminarayana":[109],"1998).":[112],"implementations":[114],"generated":[115,216],"exploit":[119],"germane":[122],"in":[123,133,155,214],"computation":[125,200],"execute":[127],"maximal":[128],"set":[129],"concurrently":[132],"order":[134],"reduce":[136,181],"latency":[138],"design.":[141],"The":[142],"concurrent":[143],"execution":[144],"enhances":[148],"performance":[150],"terms":[156],"delay":[159],"but":[160],"high":[161],"power":[162,182,210,213,249],"consumption":[163,183],"may":[164],"become":[165],"an":[166],"issue":[167],"when":[168],"multiple":[169],"are":[172],"executed":[173],"concurrently.":[174],"Thus,":[175],"there":[176],"need":[179],"during":[184],"CAOS-based":[186],"synthesis.":[187],"In":[188],"this":[189],"paper,":[190],"we":[191],"consider":[192],"similar":[195],"Bluespec's":[197],"model":[198],"present":[202],"two":[203],"strategies":[204],"targeting":[205],"reduction":[207,250],"peak":[209],"dynamic":[212],"specifications.":[219],"One":[220],"strategy":[221],"re-scheduling":[224,244],"generate":[230],"low-power":[232],"schedule":[233],"whereas":[234],"other":[236],"exploits":[237],"factorization":[239],"as":[240,242],"well":[241]},"counts_by_year":[{"year":2013,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}