{"id":"https://openalex.org/W4234927713","doi":"https://doi.org/10.1109/memcod.2003.1210105","title":"LOTOS code generation for model checking of STBus based SoC: the STBus interconnection","display_name":"LOTOS code generation for model checking of STBus based SoC: the STBus interconnection","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W4234927713","doi":"https://doi.org/10.1109/memcod.2003.1210105"},"language":"en","primary_location":{"id":"doi:10.1109/memcod.2003.1210105","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2003.1210105","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081708449","display_name":"P. Wodey","orcid":null},"institutions":[{"id":"https://openalex.org/I4210099416","display_name":"Laboratoire d'Informatique, de Mod\u00e9lisation et d'Optimisation des Syst\u00e8mes","ror":"https://ror.org/00t3fpp34","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I198244214","https://openalex.org/I198244214","https://openalex.org/I203339264","https://openalex.org/I205703379","https://openalex.org/I3019848993","https://openalex.org/I4210099416","https://openalex.org/I4210123221","https://openalex.org/I4210159245","https://openalex.org/I4387154249"]},{"id":"https://openalex.org/I4210104097","display_name":"Institut Sup\u00e9rieur d\u2019Informatique, de Mod\u00e9lisation et de leurs Applications","ror":"https://ror.org/01bv2n867","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210104097"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"P. Wodey","raw_affiliation_strings":["ISIMA-LIMOS, Aubiere, France"],"affiliations":[{"raw_affiliation_string":"ISIMA-LIMOS, Aubiere, France","institution_ids":["https://openalex.org/I4210099416","https://openalex.org/I4210104097"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090720797","display_name":"G. Camarroque","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104097","display_name":"Institut Sup\u00e9rieur d\u2019Informatique, de Mod\u00e9lisation et de leurs Applications","ror":"https://ror.org/01bv2n867","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210104097"]},{"id":"https://openalex.org/I4210099416","display_name":"Laboratoire d'Informatique, de Mod\u00e9lisation et d'Optimisation des Syst\u00e8mes","ror":"https://ror.org/00t3fpp34","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I198244214","https://openalex.org/I198244214","https://openalex.org/I203339264","https://openalex.org/I205703379","https://openalex.org/I3019848993","https://openalex.org/I4210099416","https://openalex.org/I4210123221","https://openalex.org/I4210159245","https://openalex.org/I4387154249"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"G. Camarroque","raw_affiliation_strings":["ISIMA-LIMOS, Aubiere, France"],"affiliations":[{"raw_affiliation_string":"ISIMA-LIMOS, Aubiere, France","institution_ids":["https://openalex.org/I4210099416","https://openalex.org/I4210104097"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079628122","display_name":"F. Baray","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104097","display_name":"Institut Sup\u00e9rieur d\u2019Informatique, de Mod\u00e9lisation et de leurs Applications","ror":"https://ror.org/01bv2n867","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210104097"]},{"id":"https://openalex.org/I4210099416","display_name":"Laboratoire d'Informatique, de Mod\u00e9lisation et d'Optimisation des Syst\u00e8mes","ror":"https://ror.org/00t3fpp34","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I198244214","https://openalex.org/I198244214","https://openalex.org/I203339264","https://openalex.org/I205703379","https://openalex.org/I3019848993","https://openalex.org/I4210099416","https://openalex.org/I4210123221","https://openalex.org/I4210159245","https://openalex.org/I4387154249"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"F. Baray","raw_affiliation_strings":["ISIMA-LIMOS, Aubiere, France"],"affiliations":[{"raw_affiliation_string":"ISIMA-LIMOS, Aubiere, France","institution_ids":["https://openalex.org/I4210099416","https://openalex.org/I4210104097"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018524547","display_name":"R. Hersemeule","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"R. Hersemeule","raw_affiliation_strings":["STMicroelectronics, Advance Systems Technology AST, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Advance Systems Technology AST, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057472215","display_name":"J.-P. Cousin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J.-P. Cousin","raw_affiliation_strings":["STMicroelectronics, Advance Systems Technology AST, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Advance Systems Technology AST, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5081708449"],"corresponding_institution_ids":["https://openalex.org/I4210099416","https://openalex.org/I4210104097"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.38197759,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"x i x 5","issue":null,"first_page":"204","last_page":"213"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8457896709442139},{"id":"https://openalex.org/keywords/toolbox","display_name":"Toolbox","score":0.7188864946365356},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7059992551803589},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.7009963393211365},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.65581876039505},{"id":"https://openalex.org/keywords/deadlock-prevention-algorithms","display_name":"Deadlock prevention algorithms","score":0.566971480846405},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5652811527252197},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5425028204917908},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.510805606842041},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4702633321285248},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.4497952461242676},{"id":"https://openalex.org/keywords/temporal-logic","display_name":"Temporal logic","score":0.44267016649246216},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.44130757451057434},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.42667290568351746},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3498057723045349},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32341182231903076},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.25139492750167847},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12233221530914307},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.10860279202461243},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08207562565803528}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8457896709442139},{"id":"https://openalex.org/C2777655017","wikidata":"https://www.wikidata.org/wiki/Q1501161","display_name":"Toolbox","level":2,"score":0.7188864946365356},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7059992551803589},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.7009963393211365},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.65581876039505},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.566971480846405},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5652811527252197},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5425028204917908},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.510805606842041},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4702633321285248},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.4497952461242676},{"id":"https://openalex.org/C25016198","wikidata":"https://www.wikidata.org/wiki/Q781833","display_name":"Temporal logic","level":2,"score":0.44267016649246216},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.44130757451057434},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.42667290568351746},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3498057723045349},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32341182231903076},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.25139492750167847},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12233221530914307},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.10860279202461243},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08207562565803528},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/memcod.2003.1210105","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2003.1210105","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1711877719","https://openalex.org/W1994350081","https://openalex.org/W2016626678","https://openalex.org/W2113639092","https://openalex.org/W6637575055"],"related_works":["https://openalex.org/W2050076411","https://openalex.org/W2001478969","https://openalex.org/W1542183432","https://openalex.org/W2360686363","https://openalex.org/W1900787600","https://openalex.org/W2136552483","https://openalex.org/W2166954426","https://openalex.org/W2117224408","https://openalex.org/W3137070212","https://openalex.org/W2379911191"],"abstract_inverted_index":{"In":[0,56,64],"the":[1,13,31,38,43,48,53,61,82,93,96,104,114,132,136,143,147,159,175,180,196,201,205,208],"design":[2],"process":[3],"of":[4,12,47,81,106,116,135,149,161,174,207],"SoC":[5,154,199],"(System":[6],"on":[7,151,195],"Chip),":[8],"validation":[9,29],"is":[10,127],"one":[11],"most":[14],"critical":[15],"and":[16,142],"costly":[17],"activity.":[18],"The":[19,122,189],"main":[20],"problem":[21],"for":[22,71,103,146],"industrial":[23],"companies":[24],"like":[25],"STMicroelectronics,":[26],"stands":[27],"in":[28,75,129,204],"at":[30,90],"complete":[32],"system":[33,54,120],"level.":[34],"At":[35],"this":[36,65],"level,":[37],"properties":[39,173],"to":[40,169,182],"verify":[41],"concern":[42],"well":[44],"behavior":[45,138],"composed":[46],"different":[49],"processes":[50,137,150],"interconnected":[51],"around":[52],"bus.":[55,155],"our":[57],"work":[58],"we":[59,67],"consider":[60],"deadlock-free":[62],"property.":[63],"paper":[66,157],"present":[68],"an":[69],"approach":[70],"deadlock":[72,166,186],"detection":[73,167,187],"consisting":[74],"generating":[76],"automatically":[77],"a":[78,117,152,184],"LOTOS":[79,97,124,209],"description":[80,98],"system.":[83],"Then,":[84],"by":[85,92],"using":[86],"CADP":[87],"toolbox":[88],"developed":[89],"INRIA":[91],"VASY":[94],"team,":[95],"can":[99],"then":[100,193],"be":[101],"used":[102],"evaluation":[105],"temporal":[107],"logic":[108],"formula,":[109],"either":[110],"on-the-fly":[111],"or":[112],"after":[113],"generation":[115,126,134,145,211],"labeled":[118],"transition":[119],"(LTS).":[121],"automatic":[123],"code":[125,133,144,210],"decomposed":[128],"two":[130],"parts,":[131],"(work":[139],"under":[140],"progress)":[141],"interconnection":[148],"given":[153],"This":[156],"presents":[158],"principles":[160,191],"interconnect":[162],"abstraction":[163],"showing":[164],"that":[165],"has":[168],"take":[170],"into":[171],"account":[172],"implemented":[176],"communication":[177],"channel,":[178],"avoiding":[179],"possibility":[181],"build":[183],"general":[185],"tool.":[188],"resulting":[190],"are":[192],"applied":[194],"STMicroelectronics":[197],"proprietary":[198],"bus,":[200],"STBus,":[202],"leading":[203],"development":[206],"software.":[212]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
