{"id":"https://openalex.org/W4233555437","doi":"https://doi.org/10.1109/memcod.2003.1210090","title":"Formal verification of an Intel XScale processor model with scoreboarding, specialized execution pipelines, and impress data-memory exceptions","display_name":"Formal verification of an Intel XScale processor model with scoreboarding, specialized execution pipelines, and impress data-memory exceptions","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W4233555437","doi":"https://doi.org/10.1109/memcod.2003.1210090"},"language":"en","primary_location":{"id":"doi:10.1109/memcod.2003.1210090","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2003.1210090","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033170576","display_name":"Sudarshan K. Srinivasan","orcid":"https://orcid.org/0000-0001-7040-384X"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S.K. Srinivasan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030659202","display_name":"Miroslav N. Velev","orcid":"https://orcid.org/0000-0001-7775-5186"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.N. Velev","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5033170576"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":1.0062,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.7899659,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2031","issue":null,"first_page":"65","last_page":"74"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8271665573120117},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4999198913574219},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.47595641016960144},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4700015187263489},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4556988477706909},{"id":"https://openalex.org/keywords/pipeline-transport","display_name":"Pipeline transport","score":0.45027345418930054},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4338788688182831},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.37992554903030396},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36931487917900085}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8271665573120117},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4999198913574219},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.47595641016960144},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4700015187263489},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4556988477706909},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.45027345418930054},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4338788688182831},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.37992554903030396},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36931487917900085},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/memcod.2003.1210090","is_oa":false,"landing_page_url":"https://doi.org/10.1109/memcod.2003.1210090","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6800000071525574,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W5325007","https://openalex.org/W71238222","https://openalex.org/W1494093576","https://openalex.org/W1506611120","https://openalex.org/W1521083034","https://openalex.org/W1525387472","https://openalex.org/W1563319185","https://openalex.org/W1574024214","https://openalex.org/W1579968042","https://openalex.org/W1583532098","https://openalex.org/W1588758388","https://openalex.org/W1599897266","https://openalex.org/W1601250460","https://openalex.org/W1782705083","https://openalex.org/W1903118409","https://openalex.org/W1959350751","https://openalex.org/W1979072566","https://openalex.org/W2006120207","https://openalex.org/W2010880586","https://openalex.org/W2026275875","https://openalex.org/W2063162149","https://openalex.org/W2087702998","https://openalex.org/W2110011370","https://openalex.org/W2113002954","https://openalex.org/W2123905682","https://openalex.org/W2163820265","https://openalex.org/W2255090137","https://openalex.org/W2535164759","https://openalex.org/W2617531914","https://openalex.org/W4247585869","https://openalex.org/W4250620173","https://openalex.org/W4253744987","https://openalex.org/W6630699798","https://openalex.org/W6631200409","https://openalex.org/W6635248543","https://openalex.org/W6635949539","https://openalex.org/W6637892366","https://openalex.org/W6639565781","https://openalex.org/W6672423286","https://openalex.org/W6677134864","https://openalex.org/W6683865707","https://openalex.org/W6692201768","https://openalex.org/W7047247977"],"related_works":["https://openalex.org/W1995889332","https://openalex.org/W3104163240","https://openalex.org/W3008693296","https://openalex.org/W4312283151","https://openalex.org/W2381158465","https://openalex.org/W2617721340","https://openalex.org/W2507253542","https://openalex.org/W3043674730","https://openalex.org/W2327589517","https://openalex.org/W1978012318"],"abstract_inverted_index":{"We":[0],"present":[1],"the":[2,68,73],"formal":[3,56],"verification":[4,57],"of":[5,45,67],"an":[6,61,78],"Intel":[7],"Xscale":[8,12],"processor":[9,17,29],"model.":[10],"The":[11,28,55],"is":[13],"a":[14],"superpipelined":[15],"RISC":[16],"with":[18,60],"7-stage":[19],"integer,":[20],"8-stage":[21],"memory,":[22],"and":[23,36,40,51,77],"variable-latency":[24],"multiply-and-accumulate":[25],"execution":[26],"pipelines.":[27],"uses":[30],"scoreboarding":[31],"to":[32],"track":[33],"data":[34],"dependencies,":[35],"implements":[37],"both":[38],"precise":[39],"imprecise":[41],"exceptions.":[42],"Such":[43],"set":[44],"features":[46],"had":[47],"not":[48],"been":[49],"modeled":[50],"formally":[52],"verified":[53],"previously.":[54],"was":[58],"done":[59],"automatic":[62],"tool":[63],"flow":[64],"that":[65],"consists":[66],"term-level":[69],"symbolic":[70],"simulator":[71],"TLSim,":[72],"decision":[74],"procedure":[75],"EVC,":[76],"efficient":[79],"SAT-checker.":[80]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
