{"id":"https://openalex.org/W2881234030","doi":"https://doi.org/10.1109/meco.2018.8406096","title":"Asynchronous logic design targeting LUTs","display_name":"Asynchronous logic design targeting LUTs","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2881234030","doi":"https://doi.org/10.1109/meco.2018.8406096","mag":"2881234030"},"language":"en","primary_location":{"id":"doi:10.1109/meco.2018.8406096","is_oa":false,"landing_page_url":"https://doi.org/10.1109/meco.2018.8406096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 7th Mediterranean Conference on Embedded Computing (MECO)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081940001","display_name":"Igor Lemberski","orcid":"https://orcid.org/0000-0001-9596-1506"},"institutions":[{"id":"https://openalex.org/I926082481","display_name":"Ventspils University of Applied Sciences","ror":"https://ror.org/03sc6wx59","country_code":"LV","type":"education","lineage":["https://openalex.org/I926082481"]}],"countries":["LV"],"is_corresponding":true,"raw_author_name":"Igor Lemberski","raw_affiliation_strings":["International Radio Astronomy Centre, Ventspils University College, Ventspils, Latvia"],"affiliations":[{"raw_affiliation_string":"International Radio Astronomy Centre, Ventspils University College, Ventspils, Latvia","institution_ids":["https://openalex.org/I926082481"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060252834","display_name":"Artjoms Supo\u0146enkovs","orcid":"https://orcid.org/0000-0002-1463-8166"},"institutions":[{"id":"https://openalex.org/I926082481","display_name":"Ventspils University of Applied Sciences","ror":"https://ror.org/03sc6wx59","country_code":"LV","type":"education","lineage":["https://openalex.org/I926082481"]}],"countries":["LV"],"is_corresponding":false,"raw_author_name":"Artjoms Suponenkovs","raw_affiliation_strings":["International Radio Astronomy Centre, Ventspils University College, Ventspils, Latvia"],"affiliations":[{"raw_affiliation_string":"International Radio Astronomy Centre, Ventspils University College, Ventspils, Latvia","institution_ids":["https://openalex.org/I926082481"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5081940001"],"corresponding_institution_ids":["https://openalex.org/I926082481"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.47255064,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.813920259475708},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7419640421867371},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.558999240398407},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.48755353689193726},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.47130143642425537},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.45848792791366577},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.4535650908946991},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.443460613489151},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.43113693594932556},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4104927182197571},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3542419672012329},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.35071903467178345},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3474808931350708},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.32194948196411133},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15621325373649597},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.13296666741371155},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11038953065872192}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.813920259475708},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7419640421867371},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.558999240398407},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.48755353689193726},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.47130143642425537},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.45848792791366577},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.4535650908946991},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.443460613489151},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.43113693594932556},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4104927182197571},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3542419672012329},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.35071903467178345},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3474808931350708},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.32194948196411133},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15621325373649597},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.13296666741371155},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11038953065872192},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/meco.2018.8406096","is_oa":false,"landing_page_url":"https://doi.org/10.1109/meco.2018.8406096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 7th Mediterranean Conference on Embedded Computing (MECO)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1484446818","https://openalex.org/W1514480347","https://openalex.org/W1979898771","https://openalex.org/W1987360731","https://openalex.org/W2015420475","https://openalex.org/W2028438402","https://openalex.org/W2081240624","https://openalex.org/W2105761964","https://openalex.org/W2116912398","https://openalex.org/W2125625632","https://openalex.org/W2137978379","https://openalex.org/W4242865834","https://openalex.org/W4247600734","https://openalex.org/W6630761995","https://openalex.org/W6645280798","https://openalex.org/W6676111922","https://openalex.org/W6678608396"],"related_works":["https://openalex.org/W2053477566","https://openalex.org/W1966764473","https://openalex.org/W2141712138","https://openalex.org/W2098419840","https://openalex.org/W2614722573","https://openalex.org/W2356140560","https://openalex.org/W2121963733","https://openalex.org/W2789349722","https://openalex.org/W4379115868","https://openalex.org/W2370649629"],"abstract_inverted_index":{"The":[0,160],"conventional":[1,77],"approach":[2],"to":[3,36,86,172],"logic":[4,60],"design":[5,38,62],"targeting":[6,63,141],"LUTs":[7,22],"of":[8,32,65,69,138,180,186],"limited":[9],"inputs":[10,34],"number":[11,35,143],"is":[12,71,74,83,99,145,162,176,191,200],"oriented":[13,128],"on":[14,76,129,153],"multi-level":[15],"decomposition.":[16],"Nowadays":[17],"reconfigurable":[18],"chips":[19],"contain":[20],"multiple":[21],"that":[23,101,156],"can":[24,45],"be":[25,46],"combined.":[26],"It":[27,73,98],"implies":[28],"producing":[29,121],"LUT-based":[30],"structure":[31],"various":[33],"match":[37],"needs.":[39],"As":[40],"a":[41,43,165],"result,":[42],"function":[44,61],"implemented":[47],"using":[48],"one-level":[49],"LUT":[50,64,102,115,198],"which":[51],"increases":[52],"circuit":[53],"performance.":[54],"In":[55,133],"the":[56,134,136,174],"paper,":[57,135],"asynchronous":[58],"dual-rail":[59],"minimal":[66],"size":[67,199],"(number":[68],"inputs)":[70],"proposed.":[72,146,177],"based":[75],"Sum-Of-Product":[78],"terms":[79],"(SOP)":[80],"functions":[81],"what":[82],"in":[84],"contrast":[85],"existing":[87,117],"methods":[88,118],"where":[89],"Sum-Of-Minterms":[90],"(SOM)":[91],"and":[92,105,119,184,188],"Disjoint":[93],"SOP":[94,108,112,122,140,189],"representations":[95],"are":[96,126,151,182],"considered.":[97],"shown,":[100],"architectural":[103],"features":[104],"delays":[106],"ensure":[107],"hazard-free":[109],"implementation.":[110],"Although":[111],"representation":[113],"reduces":[114],"size,":[116],"tools":[120],"(for":[123],"example,":[124],"Espresso)":[125],"primary":[127],"product":[130,157],"term":[131],"minimization.":[132,159],"method":[137],"generating":[139],"literal":[142,154],"minimization":[144],"Within":[147],"this":[148],"method,":[149,195],"efforts":[150],"focused":[152],"(rather":[155],"term)":[158],"task":[161],"formulated":[163],"as":[164],"unate":[166],"covering":[167],"problem.":[168],"A":[169],"heuristic":[170],"algorithm":[171],"solve":[173],"problem":[175],"Two":[178],"sets":[179],"benchmarks":[181],"processed":[183],"comparison":[185],"SOM":[187],"implementations":[190],"done.":[192],"Using":[193],"our":[194],"improvement":[196],"w.r.t.":[197],"achieved.":[201]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-25T21:42:39.735039","created_date":"2025-10-10T00:00:00"}