{"id":"https://openalex.org/W2734659723","doi":"https://doi.org/10.1109/meco.2017.7977125","title":"SWL algorithms optimization using alternative adder module in FPGA","display_name":"SWL algorithms optimization using alternative adder module in FPGA","publication_year":2017,"publication_date":"2017-06-01","ids":{"openalex":"https://openalex.org/W2734659723","doi":"https://doi.org/10.1109/meco.2017.7977125","mag":"2734659723"},"language":"en","primary_location":{"id":"doi:10.1109/meco.2017.7977125","is_oa":false,"landing_page_url":"https://doi.org/10.1109/meco.2017.7977125","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 6th Mediterranean Conference on Embedded Computing (MECO)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067324884","display_name":"Tayab Din Memon","orcid":"https://orcid.org/0000-0001-8122-5647"},"institutions":[{"id":"https://openalex.org/I180291457","display_name":"Mehran University of Engineering and Technology","ror":"https://ror.org/0575ttm03","country_code":"PK","type":"education","lineage":["https://openalex.org/I180291457"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Tayab D. Memon","raw_affiliation_strings":["Department of Electronics, Mehran UET, Jamshoro, Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Mehran UET, Jamshoro, Pakistan","institution_ids":["https://openalex.org/I180291457"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016001290","display_name":"Shaji Farooq Baig","orcid":null},"institutions":[{"id":"https://openalex.org/I180291457","display_name":"Mehran University of Engineering and Technology","ror":"https://ror.org/0575ttm03","country_code":"PK","type":"education","lineage":["https://openalex.org/I180291457"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Shaji Farooq Baig","raw_affiliation_strings":["Department of Electronics, Mehran UET, Jamshoro, Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Mehran UET, Jamshoro, Pakistan","institution_ids":["https://openalex.org/I180291457"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011066035","display_name":"Marvi Deshi","orcid":null},"institutions":[{"id":"https://openalex.org/I180291457","display_name":"Mehran University of Engineering and Technology","ror":"https://ror.org/0575ttm03","country_code":"PK","type":"education","lineage":["https://openalex.org/I180291457"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Marvi Deshi","raw_affiliation_strings":["Department of Electronics, Mehran UET, Jamshoro, Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Mehran UET, Jamshoro, Pakistan","institution_ids":["https://openalex.org/I180291457"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082676919","display_name":"Imtiaz Hussain Kalwar","orcid":"https://orcid.org/0000-0002-7947-9178"},"institutions":[{"id":"https://openalex.org/I180291457","display_name":"Mehran University of Engineering and Technology","ror":"https://ror.org/0575ttm03","country_code":"PK","type":"education","lineage":["https://openalex.org/I180291457"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Imtiaz Hussain Kalwar","raw_affiliation_strings":["Department of Electronics, Mehran UET, Jamshoro, Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Mehran UET, Jamshoro, Pakistan","institution_ids":["https://openalex.org/I180291457"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I180291457"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"70","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11233","display_name":"Advanced Adaptive Filtering Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9400249719619751},{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.9166479110717773},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.7355093955993652},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.667219877243042},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6538315415382385},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5257806777954102},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.5198481678962708},{"id":"https://openalex.org/keywords/ternary-operation","display_name":"Ternary operation","score":0.4651888906955719},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.42748820781707764},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.41911035776138306},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.41741758584976196},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4084286093711853},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.38081878423690796},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3546825647354126},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2324962615966797},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.22285884618759155},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0962156355381012},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.08043676614761353}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9400249719619751},{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.9166479110717773},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.7355093955993652},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.667219877243042},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6538315415382385},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5257806777954102},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.5198481678962708},{"id":"https://openalex.org/C64452783","wikidata":"https://www.wikidata.org/wiki/Q1524945","display_name":"Ternary operation","level":2,"score":0.4651888906955719},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.42748820781707764},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.41911035776138306},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.41741758584976196},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4084286093711853},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.38081878423690796},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3546825647354126},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2324962615966797},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.22285884618759155},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0962156355381012},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.08043676614761353},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/meco.2017.7977125","is_oa":false,"landing_page_url":"https://doi.org/10.1109/meco.2017.7977125","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 6th Mediterranean Conference on Embedded Computing (MECO)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1972959261","https://openalex.org/W2025517455","https://openalex.org/W2032152253","https://openalex.org/W2052099679","https://openalex.org/W2059240421","https://openalex.org/W2065336837","https://openalex.org/W2088495138","https://openalex.org/W2108631315","https://openalex.org/W2131222732","https://openalex.org/W6643494207","https://openalex.org/W6679384362"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W3119693822","https://openalex.org/W2560648274","https://openalex.org/W3021100968","https://openalex.org/W2188712114"],"abstract_inverted_index":{"Recently":[0],"single-bit":[1],"ternary":[2,37,44],"FIR-like":[3],"filter":[4,17,29],"(SBTFF)":[5],"hardware":[6],"synthesize":[7,84],"in":[8,50,59,69,81],"FPGA":[9],"is":[10,57,104],"reported":[11],"and":[12,47,64,127],"compared":[13,75,109],"with":[14,97],"multi-bit":[15,28],"FIR":[16],"on":[18],"similar":[19],"spectral":[20],"characteristics.":[21],"Results":[22],"shows":[23],"that":[24,87],"SBTFF":[25],"dominates":[26],"upon":[27],"overall.":[30],"In":[31],"this":[32],"work,":[33],"we":[34],"have":[35],"adopted":[36],"sigma-delta":[38],"modulated":[39],"arithmetic":[40],"adder":[41,45,78],"(i.e.,":[42],"improved":[43],"(ITA))":[46],"simulated":[48],"it":[49,56],"ModelSim":[51],"for":[52,61,125],"functional":[53],"verification.":[54],"Further,":[55],"synthesized":[58],"Xilinx":[60],"chip":[62,99],"cost":[63],"its":[65,102],"maximum":[66],"performance":[67,103],"measured":[68],"(F":[70],"<sub":[71],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[72],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">MAX</sub>":[73],")":[74],"to":[76,110],"conventional":[77,111],"module":[79],"used":[80],"SBTFF.":[82],"The":[83],"results":[85,114],"show":[86],"ITA":[88],"performs":[89],"excellent":[90],"while":[91],"inputs":[92,108],"are":[93],"higher":[94],"than":[95],"64":[96],"lower":[98,107],"areas,":[100],"whereas":[101],"poor":[105],"at":[106],"adder.":[112],"These":[113],"enhance":[115],"the":[116],"usefulness":[117],"of":[118],"existing":[119],"short":[120],"word":[121],"length":[122],"DSP":[123],"algorithms":[124],"fast":[126],"efficient":[128],"mobile":[129],"communication.":[130]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}