{"id":"https://openalex.org/W2489638043","doi":"https://doi.org/10.1109/meco.2016.7525742","title":"An approach to design-for-testability automation of analogue integrated circuits using OBIST strategy","display_name":"An approach to design-for-testability automation of analogue integrated circuits using OBIST strategy","publication_year":2016,"publication_date":"2016-06-01","ids":{"openalex":"https://openalex.org/W2489638043","doi":"https://doi.org/10.1109/meco.2016.7525742","mag":"2489638043"},"language":"en","primary_location":{"id":"doi:10.1109/meco.2016.7525742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/meco.2016.7525742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 5th Mediterranean Conference on Embedded Computing (MECO)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019089975","display_name":"Sergey Mosin","orcid":"https://orcid.org/0000-0003-1389-2602"},"institutions":[{"id":"https://openalex.org/I21203515","display_name":"Kazan Federal University","ror":"https://ror.org/05256ym39","country_code":"RU","type":"education","lineage":["https://openalex.org/I21203515"]}],"countries":["RU"],"is_corresponding":true,"raw_author_name":"Sergey Mosin","raw_affiliation_strings":["Institute of Computational Mathematics and Information Technologies, Kazan Federal University, Kazan, Russian Federation"],"affiliations":[{"raw_affiliation_string":"Institute of Computational Mathematics and Information Technologies, Kazan Federal University, Kazan, Russian Federation","institution_ids":["https://openalex.org/I21203515"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5019089975"],"corresponding_institution_ids":["https://openalex.org/I21203515"],"apc_list":null,"apc_paid":null,"fwci":0.6307,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.66879819,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"43","issue":null,"first_page":"211","last_page":"214"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.7828763723373413},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7538582682609558},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7213074564933777},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6715387105941772},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.6238650679588318},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.6047370433807373},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5746808052062988},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.5722092390060425},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4440886676311493},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.4333816170692444},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4278722107410431},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.41114968061447144},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.4107682704925537},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.40356847643852234},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.372580349445343},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3646268844604492},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.35582953691482544},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26719653606414795},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21706366539001465},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1864641010761261},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.17703169584274292},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15170538425445557},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08480769395828247}],"concepts":[{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.7828763723373413},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7538582682609558},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7213074564933777},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6715387105941772},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.6238650679588318},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.6047370433807373},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5746808052062988},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.5722092390060425},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4440886676311493},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4333816170692444},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4278722107410431},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.41114968061447144},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.4107682704925537},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.40356847643852234},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.372580349445343},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3646268844604492},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.35582953691482544},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26719653606414795},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21706366539001465},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1864641010761261},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.17703169584274292},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15170538425445557},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08480769395828247},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/meco.2016.7525742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/meco.2016.7525742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 5th Mediterranean Conference on Embedded Computing (MECO)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1969278872","https://openalex.org/W1971291179","https://openalex.org/W2026640172","https://openalex.org/W2083703696","https://openalex.org/W2124912253","https://openalex.org/W2151874577","https://openalex.org/W2156960698","https://openalex.org/W2158977975"],"related_works":["https://openalex.org/W2059530328","https://openalex.org/W3011978806","https://openalex.org/W2743305891","https://openalex.org/W3205162826","https://openalex.org/W3207169898","https://openalex.org/W3198354237","https://openalex.org/W2951650892","https://openalex.org/W2331259470","https://openalex.org/W2489638043","https://openalex.org/W1596716095"],"abstract_inverted_index":{"This":[0],"paper":[1],"is":[2,50],"mainly":[3],"focused":[4],"on":[5,14],"the":[6,53,59],"task":[7],"of":[8,36,45,72],"design-for-testability":[9],"(DFT)":[10],"automation":[11,60],"with":[12],"emphasis":[13],"OBIST":[15],"strategy":[16],"for":[17,34,47,67,75],"analog":[18],"integrated":[19],"circuits.":[20],"The":[21,43,64],"design":[22],"procedures":[23],"according":[24],"to":[25],"DFT":[26,62],"flow":[27],"are":[28,41],"proposed.":[29],"Three":[30],"possible":[31],"structural":[32],"solutions":[33],"reconfiguration":[35],"original":[37],"circuit":[38],"into":[39],"oscillator":[40],"considered.":[42],"set":[44],"rules":[46],"each":[48],"solution":[49],"prepared":[51],"as":[52],"formal":[54],"procedures,":[55],"which":[56],"can":[57],"support":[58],"during":[61],"flow.":[63],"experimental":[65],"results":[66],"three":[68],"cases":[69],"demonstrate":[70],"adequacy":[71],"oscillation":[73],"frequency":[74],"revealing":[76],"catastrophic":[77],"and":[78],"parametric":[79],"faults.":[80]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}