{"id":"https://openalex.org/W2035698524","doi":"https://doi.org/10.1109/mdt.2007.56","title":"Roundtable: Envisioning the Future for Multiprocessor SoC","display_name":"Roundtable: Envisioning the Future for Multiprocessor SoC","publication_year":2007,"publication_date":"2007-02-01","ids":{"openalex":"https://openalex.org/W2035698524","doi":"https://doi.org/10.1109/mdt.2007.56","mag":"2035698524"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2007.56","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2007.56","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113780350","display_name":"Ahmed Jerraya","orcid":null},"institutions":[{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I4210150049","display_name":"Laboratoire d'\u00c9lectronique des Technologies de l'Information","ror":"https://ror.org/04mf0wv34","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I4210117989","https://openalex.org/I4210150049"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Ahmed Amine Jerraya","raw_affiliation_strings":["CEA-Leti"],"affiliations":[{"raw_affiliation_string":"CEA-Leti","institution_ids":["https://openalex.org/I4210150049","https://openalex.org/I2738703131"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066591464","display_name":"Olivier Franza","orcid":"https://orcid.org/0009-0007-0803-9064"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Olivier Franza","raw_affiliation_strings":["Intel","Intel#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060980425","display_name":"Markus Levy","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Markus Levy","raw_affiliation_strings":["The Multicore Association and EEMBC"],"affiliations":[{"raw_affiliation_string":"The Multicore Association and EEMBC","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030360875","display_name":"M. Nakaya","orcid":null},"institutions":[{"id":"https://openalex.org/I75636454","display_name":"Renesas Electronics (United States)","ror":"https://ror.org/014775w70","country_code":"US","type":"company","lineage":["https://openalex.org/I4210153176","https://openalex.org/I75636454"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Masao Nakaya","raw_affiliation_strings":["Renesas Technology","Renesas Technology#TAB#"],"affiliations":[{"raw_affiliation_string":"Renesas Technology","institution_ids":["https://openalex.org/I75636454"]},{"raw_affiliation_string":"Renesas Technology#TAB#","institution_ids":["https://openalex.org/I75636454"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073518200","display_name":"Pierre Paulin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210124177","display_name":"STMicroelectronics (Czechia)","ror":"https://ror.org/03c7ss521","country_code":"CZ","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210124177"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Pierre Paulin","raw_affiliation_strings":["STMicroelectronics"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics","institution_ids":["https://openalex.org/I4210124177"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070106663","display_name":"Ulrich Ramacher","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]},{"id":"https://openalex.org/I4210105601","display_name":"Infineon Technologies (United Kingdom)","ror":"https://ror.org/017ptvx95","country_code":"GB","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210105601"]}],"countries":["DE","GB"],"is_corresponding":false,"raw_author_name":"Ulrich Ramacher","raw_affiliation_strings":["Infineon Technologies","Infineon Technologies,"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies","institution_ids":["https://openalex.org/I4210105601"]},{"raw_affiliation_string":"Infineon Technologies,","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038727551","display_name":"Deepu Talla","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deepu Talla","raw_affiliation_strings":["Texas Instruments"],"affiliations":[{"raw_affiliation_string":"Texas Instruments","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5104057467","display_name":"Wayne Wolf","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wayne Wolf","raw_affiliation_strings":["Princeton University","Princeton University#TAB#"],"affiliations":[{"raw_affiliation_string":"Princeton University","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University#TAB#","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":5,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5113780350"],"corresponding_institution_ids":["https://openalex.org/I2738703131","https://openalex.org/I4210150049"],"apc_list":null,"apc_paid":null,"fwci":1.9,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.85694403,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":"24","issue":"2","first_page":"174","last_page":"183"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.8120052814483643},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6563984751701355},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6070042848587036},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5548937916755676},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5117452144622803},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.43503010272979736},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21451252698898315}],"concepts":[{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.8120052814483643},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6563984751701355},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6070042848587036},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5548937916755676},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5117452144622803},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.43503010272979736},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21451252698898315}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdt.2007.56","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2007.56","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2051367001","https://openalex.org/W2170132667","https://openalex.org/W2283291034","https://openalex.org/W2158075784","https://openalex.org/W2360740901","https://openalex.org/W2021050177","https://openalex.org/W1733143018","https://openalex.org/W2105876736","https://openalex.org/W2374612118","https://openalex.org/W1923615342"],"abstract_inverted_index":{"Multiprocessor":[0],"SoCs":[1,14],"are":[2,28],"no":[3],"longer":[4],"an":[5],"advanced":[6],"research":[7],"topic":[8],"for":[9],"academia.":[10],"Ninety":[11],"percent":[12],"of":[13],"designed":[15],"in":[16],"130-nm":[17],"technology":[18],"include":[19],"at":[20],"least":[21],"one":[22],"CPU.":[23],"Most":[24],"popular":[25],"multimedia":[26],"platforms":[27],"already":[29],"multiprocessor":[30],"SoCs.":[31],"This":[32],"roundtable":[33],"brings":[34],"together":[35],"key":[36],"players":[37],"from":[38],"the":[39,46],"semiconductor":[40],"industry":[41],"and":[42,48],"academia":[43],"to":[44],"discuss":[45],"challenges":[47],"opportunities":[49],"involved":[50],"with":[51],"this":[52],"new":[53],"technology.":[54]},"counts_by_year":[{"year":2013,"cited_by_count":3}],"updated_date":"2026-02-27T16:54:17.756197","created_date":"2025-10-10T00:00:00"}
