{"id":"https://openalex.org/W2167613249","doi":"https://doi.org/10.1109/mdt.2004.1277905","title":"A top-down methodology for microprocessor validation","display_name":"A top-down methodology for microprocessor validation","publication_year":2004,"publication_date":"2004-03-01","ids":{"openalex":"https://openalex.org/W2167613249","doi":"https://doi.org/10.1109/mdt.2004.1277905","mag":"2167613249"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2004.1277905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2004.1277905","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006818844","display_name":"Prabhat Mishra","orcid":"https://orcid.org/0000-0003-3653-6221"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Mishra","raw_affiliation_strings":["University of California, Irvine","University of California, Irvine, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Irvine","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007817952","display_name":"Nikil Dutt","orcid":"https://orcid.org/0000-0002-3060-8119"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]},{"id":"https://openalex.org/I4210140791","display_name":"Irvine University","ror":"https://ror.org/04ysmca02","country_code":"US","type":"education","lineage":["https://openalex.org/I4210140791"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nikil Dutt","raw_affiliation_strings":["University of California, Irvine","University of California, Irvine, USA","California Univ., Irvine, CA (USA)"],"affiliations":[{"raw_affiliation_string":"University of California, Irvine","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"California Univ., Irvine, CA (USA)","institution_ids":["https://openalex.org/I4210140791"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112415263","display_name":"Narayanan Krishnamurthy","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N. Krishnamurthy","raw_affiliation_strings":["Motorola, Switzerland"],"affiliations":[{"raw_affiliation_string":"Motorola, Switzerland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011349515","display_name":"Magdy S. Abadir","orcid":"https://orcid.org/0000-0003-4046-2472"},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.S. Abadir","raw_affiliation_strings":["[Motorola]"],"affiliations":[{"raw_affiliation_string":"[Motorola]","institution_ids":["https://openalex.org/I1333370159"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5006818844"],"corresponding_institution_ids":["https://openalex.org/I204250578"],"apc_list":null,"apc_paid":null,"fwci":3.0343,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.91586716,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"21","issue":"2","first_page":"122","last_page":"131"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7595421671867371},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.6787816286087036},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6484670042991638},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.6454514861106873},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5956276059150696},{"id":"https://openalex.org/keywords/formal-specification","display_name":"Formal specification","score":0.5921480059623718},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.5617516040802002},{"id":"https://openalex.org/keywords/assertion","display_name":"Assertion","score":0.5374869108200073},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.49422338604927063},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.47092050313949585},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.456175297498703},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.44452521204948425},{"id":"https://openalex.org/keywords/symbolic-trajectory-evaluation","display_name":"Symbolic trajectory evaluation","score":0.44000959396362305},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33903199434280396},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.22062206268310547},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.13293012976646423},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.11226746439933777}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7595421671867371},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.6787816286087036},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6484670042991638},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.6454514861106873},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5956276059150696},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.5921480059623718},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.5617516040802002},{"id":"https://openalex.org/C40422974","wikidata":"https://www.wikidata.org/wiki/Q741248","display_name":"Assertion","level":2,"score":0.5374869108200073},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.49422338604927063},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.47092050313949585},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.456175297498703},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.44452521204948425},{"id":"https://openalex.org/C23123167","wikidata":"https://www.wikidata.org/wiki/Q7661193","display_name":"Symbolic trajectory evaluation","level":3,"score":0.44000959396362305},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33903199434280396},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.22062206268310547},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.13293012976646423},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.11226746439933777},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdt.2004.1277905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2004.1277905","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1592819458","https://openalex.org/W1986558678","https://openalex.org/W2000498093","https://openalex.org/W2010074783","https://openalex.org/W2044621917","https://openalex.org/W2109355243","https://openalex.org/W2137474858","https://openalex.org/W2146147106","https://openalex.org/W2149968564","https://openalex.org/W2157328413","https://openalex.org/W2159099907","https://openalex.org/W4243217047","https://openalex.org/W4250132578","https://openalex.org/W4251211631","https://openalex.org/W6824396207"],"related_works":["https://openalex.org/W3023586562","https://openalex.org/W2106507440","https://openalex.org/W3120172095","https://openalex.org/W2162615969","https://openalex.org/W1928822090","https://openalex.org/W2105593427","https://openalex.org/W1972950378","https://openalex.org/W2611035055","https://openalex.org/W4375857205","https://openalex.org/W1496505755"],"abstract_inverted_index":{"A":[0],"major":[1],"challenge":[2],"in":[3],"today's":[4],"functional":[5],"verification":[6,26],"is":[7,41],"the":[8,18,35],"lack":[9],"of":[10,31],"a":[11,23,32],"formal":[12],"specification":[13,30],"with":[14],"which":[15],"to":[16,43,64],"compare":[17],"RTL":[19,49,67],"model.":[20],"We":[21,52],"propose":[22],"novel":[24],"top-down":[25],"approach":[27],"that":[28,55],"allows":[29],"design":[33,68],"above":[34],"RTL.":[36],"From":[37],"this":[38],"specification,":[39],"it":[40],"possible":[42],"automatically":[44],"generate":[45],"assertion":[46],"models":[47],"and":[48,58],"reference":[50],"models.":[51],"also":[53],"demonstrate":[54],"symbolic":[56],"simulation":[57],"equivalence":[59],"checking":[60],"can":[61],"be":[62],"applied":[63],"verify":[65],"an":[66],"against":[69],"its":[70],"specification.":[71]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}