{"id":"https://openalex.org/W2157533144","doi":"https://doi.org/10.1109/mdt.2003.1214348","title":"Solving satisfiability in combinational circuits","display_name":"Solving satisfiability in combinational circuits","publication_year":2003,"publication_date":"2003-07-01","ids":{"openalex":"https://openalex.org/W2157533144","doi":"https://doi.org/10.1109/mdt.2003.1214348","mag":"2157533144"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2003.1214348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2003.1214348","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002246957","display_name":"Jo\u00e3o Marques\u2010Silva","orcid":"https://orcid.org/0000-0002-6632-3086"},"institutions":[{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. Marques-Silva","raw_affiliation_strings":["Technical University of Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Lisbon, Portugal","institution_ids":["https://openalex.org/I141596103","https://openalex.org/I203847022"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074463063","display_name":"Lu\u00eds Guerra e Silva","orcid":"https://orcid.org/0000-0001-5761-0131"},"institutions":[{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"L. Guerra e Silva","raw_affiliation_strings":["Technical University of Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Lisbon, Portugal","institution_ids":["https://openalex.org/I141596103","https://openalex.org/I203847022"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.0145,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.87873506,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"20","issue":"4","first_page":"16","last_page":"21"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.8190242052078247},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.7383418083190918},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6831724643707275},{"id":"https://openalex.org/keywords/satisfiability","display_name":"Satisfiability","score":0.6596019864082336},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.5822787880897522},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.532811164855957},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4833076000213623},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.46407416462898254},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.45041322708129883},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.4354093670845032},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.42405444383621216},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4112549424171448},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3896873891353607},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1364770233631134},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12383535504341125}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.8190242052078247},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.7383418083190918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6831724643707275},{"id":"https://openalex.org/C168773769","wikidata":"https://www.wikidata.org/wiki/Q1350299","display_name":"Satisfiability","level":2,"score":0.6596019864082336},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.5822787880897522},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.532811164855957},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4833076000213623},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.46407416462898254},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.45041322708129883},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.4354093670845032},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.42405444383621216},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4112549424171448},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3896873891353607},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1364770233631134},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12383535504341125},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/mdt.2003.1214348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2003.1214348","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},{"id":"pmh:oai:eprints.soton.ac.uk:262063","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306401019","display_name":"ePrints Soton (University of Southampton)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I43439940","host_organization_name":"University of Southampton","host_organization_lineage":["https://openalex.org/I43439940"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W33927306","https://openalex.org/W1554885925","https://openalex.org/W1855994541","https://openalex.org/W2048051309","https://openalex.org/W2051111453","https://openalex.org/W2062897452","https://openalex.org/W2075959177","https://openalex.org/W2098335680","https://openalex.org/W2108637261","https://openalex.org/W2142785340","https://openalex.org/W2149968564","https://openalex.org/W2533858263","https://openalex.org/W3147914313","https://openalex.org/W4229840182","https://openalex.org/W4247585869","https://openalex.org/W4251211631","https://openalex.org/W4285719527","https://openalex.org/W4302458519","https://openalex.org/W6676297544"],"related_works":["https://openalex.org/W2117563988","https://openalex.org/W2120257283","https://openalex.org/W2132684947","https://openalex.org/W1412895167","https://openalex.org/W2019500818","https://openalex.org/W2165817266","https://openalex.org/W2360180534","https://openalex.org/W2127167802","https://openalex.org/W2109674123","https://openalex.org/W2157533144"],"abstract_inverted_index":{"As":[0],"EDA":[1],"evolves,":[2],"researchers":[3],"continue":[4],"to":[5,9,63],"find":[6],"modeling":[7,25],"tools":[8],"solve":[10],"problems":[11],"of":[12],"test":[13],"generation,":[14],"design":[15],"verification,":[16],"logic,":[17],"and":[18,56],"physical":[19],"synthesis,":[20],"among":[21],"others.":[22],"One":[23],"such":[24],"tool":[26],"is":[27],"Boolean":[28],"satisfiability":[29],"(SAT),":[30],"which":[31],"has":[32],"very":[33],"broad":[34],"applicability":[35],"in":[36,53],"EDA.":[37],"The":[38],"authors":[39],"review":[40],"modern":[41],"SAT":[42],"algorithms,":[43],"show":[44],"how":[45],"these":[46],"algorithms":[47],"can":[48,61],"account":[49],"for":[50],"structural":[51],"information":[52],"combinational":[54],"circuits,":[55],"explain":[57],"what":[58],"recursive":[59],"learning":[60],"add":[62],"SAT.":[64]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
