{"id":"https://openalex.org/W2079486027","doi":"https://doi.org/10.1109/mdt.2003.1198687","title":"Embedded-memory test and repair: infrastructure IP for SoC yield","display_name":"Embedded-memory test and repair: infrastructure IP for SoC yield","publication_year":2003,"publication_date":"2003-05-01","ids":{"openalex":"https://openalex.org/W2079486027","doi":"https://doi.org/10.1109/mdt.2003.1198687","mag":"2079486027"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2003.1198687","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2003.1198687","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108606295","display_name":"Y. Zorian","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Zorian","raw_affiliation_strings":["Virage Logic","Virage Logic#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Virage Logic","institution_ids":[]},{"raw_affiliation_string":"Virage Logic#TAB#","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044147350","display_name":"S. Shoukourian","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Shoukourian","raw_affiliation_strings":["Virage Logic","Virage Logic#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Virage Logic","institution_ids":[]},{"raw_affiliation_string":"Virage Logic#TAB#","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.4352,"has_fulltext":false,"cited_by_count":160,"citation_normalized_percentile":{"value":0.94595612,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":"20","issue":"3","first_page":"58","last_page":"66"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6574720144271851},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5496115684509277},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5139352679252625},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.4102778732776642},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3358346223831177},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.32944774627685547}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6574720144271851},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5496115684509277},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5139352679252625},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.4102778732776642},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3358346223831177},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.32944774627685547},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdt.2003.1198687","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2003.1198687","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6700000166893005}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1792362277","https://openalex.org/W1922918362","https://openalex.org/W2054971791","https://openalex.org/W2096018418","https://openalex.org/W2098987953","https://openalex.org/W2100209794","https://openalex.org/W2101406832","https://openalex.org/W2122442616","https://openalex.org/W2134822007","https://openalex.org/W2156041716","https://openalex.org/W2163518473","https://openalex.org/W2503952136","https://openalex.org/W4247608823"],"related_works":["https://openalex.org/W2036806516","https://openalex.org/W1967394420","https://openalex.org/W2565425548","https://openalex.org/W2392009442","https://openalex.org/W2155685366","https://openalex.org/W2142443274","https://openalex.org/W13556768","https://openalex.org/W2912613323","https://openalex.org/W2100663632","https://openalex.org/W2031621863"],"abstract_inverted_index":{"Today's":[0],"complex":[1],"SoCs":[2],"need":[3],"sophisticated":[4],"infrastructure":[5,38],"IP,":[6],"not":[7],"only":[8],"to":[9,17],"test":[10,31],"and":[11,20,32,43,47],"diagnose":[12],"embedded":[13],"memories":[14],"but":[15],"also":[16],"repair":[18,33,45],"them":[19],"improve":[21],"fabrication":[22],"yield.":[23,50],"The":[24],"authors":[25],"solution":[26],"integrates":[27],"memory":[28],"IP":[29,34,39],"with":[30],"in":[35],"a":[36],"composite":[37],"that":[40],"ensures":[41],"manufacturing":[42],"field":[44],"efficiency":[46],"optimizes":[48],"SoC":[49]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":9},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":11},{"year":2012,"cited_by_count":15}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
