{"id":"https://openalex.org/W2127440835","doi":"https://doi.org/10.1109/mdt.2003.1188262","title":"A design-for-verification technique for functional pattern reduction","display_name":"A design-for-verification technique for functional pattern reduction","publication_year":2003,"publication_date":"2003-03-01","ids":{"openalex":"https://openalex.org/W2127440835","doi":"https://doi.org/10.1109/mdt.2003.1188262","mag":"2127440835"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2003.1188262","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2003.1188262","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052798292","display_name":"Chien\u2010Nan Jimmy Liu","orcid":"https://orcid.org/0000-0002-4907-898X"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chien-Nan Jimmy Liu","raw_affiliation_strings":["National Chiao Tung University, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103090231","display_name":"I\u2010Ling Chen","orcid":"https://orcid.org/0000-0003-1270-4198"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"I-Ling Chen","raw_affiliation_strings":["National Chiao Tung University, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111925764","display_name":"Jing-Yang Jou","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jing-Yang Jou","raw_affiliation_strings":["National Chiao Tung University, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5052798292"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.5031,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.67199221,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"20","issue":"2","first_page":"48","last_page":"55"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7686455249786377},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6581772565841675},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5787911415100098},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.4791490435600281},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4788912832736969},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.45205989480018616},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.440656840801239},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4228541851043701},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40081533789634705},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36726343631744385},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.3529077470302582},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3474491238594055},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3325932025909424},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1215498149394989},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.10541921854019165}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7686455249786377},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6581772565841675},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5787911415100098},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.4791490435600281},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4788912832736969},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.45205989480018616},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.440656840801239},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4228541851043701},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40081533789634705},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36726343631744385},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.3529077470302582},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3474491238594055},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3325932025909424},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1215498149394989},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.10541921854019165},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdt.2003.1188262","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2003.1188262","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320313559","display_name":"CERN","ror":"https://ror.org/01ggx4157"},{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"},{"id":"https://openalex.org/F4320323443","display_name":"National Chiao Tung University","ror":"https://ror.org/00se2k293"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1554885925","https://openalex.org/W1768820276","https://openalex.org/W2000557929","https://openalex.org/W2004917085","https://openalex.org/W2021799856","https://openalex.org/W2121557786","https://openalex.org/W2128475506","https://openalex.org/W2134626087","https://openalex.org/W2135129887","https://openalex.org/W2152077567","https://openalex.org/W4230594603","https://openalex.org/W4235989343","https://openalex.org/W4246313223","https://openalex.org/W4302458519"],"related_works":["https://openalex.org/W2105593427","https://openalex.org/W3120172095","https://openalex.org/W2118572231","https://openalex.org/W2106507440","https://openalex.org/W2108860137","https://openalex.org/W3209085687","https://openalex.org/W1928822090","https://openalex.org/W2153955347","https://openalex.org/W2533078207","https://openalex.org/W2112298791"],"abstract_inverted_index":{"This":[0],"technique":[1],"reduces":[2],"the":[3],"number":[4,42],"of":[5,43],"required":[6],"functional":[7],"patterns":[8],"by":[9,38],"first":[10],"defining":[11],"conditions":[12],"for":[13,45],"hard-to-control":[14],"(HTC)":[15],"code":[16,29],"in":[17],"a":[18,40],"hardware-description-language":[19],"design":[20],"and":[21],"then":[22],"using":[23],"an":[24],"algorithm":[25,33],"to":[26],"detect":[27],"such":[28],"automatically.":[30],"A":[31],"second":[32],"eliminates":[34],"these":[35],"HTC":[36],"points":[37],"selecting":[39],"minimum":[41],"nodes":[44],"control":[46],"point":[47],"insertion.":[48]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
