{"id":"https://openalex.org/W1994356874","doi":"https://doi.org/10.1109/mdt.2002.1033790","title":"Leakage and process variation effects in current testing on future CMOS circuits","display_name":"Leakage and process variation effects in current testing on future CMOS circuits","publication_year":2002,"publication_date":"2002-09-01","ids":{"openalex":"https://openalex.org/W1994356874","doi":"https://doi.org/10.1109/mdt.2002.1033790","mag":"1994356874"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2002.1033790","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2002.1033790","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103040522","display_name":"A. Keshavarzi","orcid":"https://orcid.org/0000-0001-6938-1161"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Keshavarzi","raw_affiliation_strings":["INTEL, Research Laboratory, USA"],"affiliations":[{"raw_affiliation_string":"INTEL, Research Laboratory, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111484157","display_name":"Jim Tschanz","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.W. Tschanz","raw_affiliation_strings":["INTEL, Research Laboratory, USA"],"affiliations":[{"raw_affiliation_string":"INTEL, Research Laboratory, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091080461","display_name":"S. Narendra","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Narendra","raw_affiliation_strings":["INTEL, Research Laboratory, USA"],"affiliations":[{"raw_affiliation_string":"INTEL, Research Laboratory, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek De","orcid":"https://orcid.org/0000-0001-5207-1079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. De","raw_affiliation_strings":["INTEL, Research Laboratory, USA"],"affiliations":[{"raw_affiliation_string":"INTEL, Research Laboratory, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001994622","display_name":"W.R. Daasch","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.R. Daasch","raw_affiliation_strings":["Purdue University, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I169521973","display_name":"University of New Mexico","ror":"https://ror.org/05fs6jp91","country_code":"US","type":"education","lineage":["https://openalex.org/I169521973"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Roy","raw_affiliation_strings":["University of New Mexico, USA"],"affiliations":[{"raw_affiliation_string":"University of New Mexico, USA","institution_ids":["https://openalex.org/I169521973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086259491","display_name":"Manoj Sachdev","orcid":"https://orcid.org/0000-0002-8256-9828"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Sachdev","raw_affiliation_strings":["Portland State University, USA"],"affiliations":[{"raw_affiliation_string":"Portland State University, USA","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111892655","display_name":"C.F. Hawkins","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"C.F. Hawkins","raw_affiliation_strings":["University of Waterloo, Canada"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Canada","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5103040522"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":4.4127,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.94804172,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"19","issue":"5","first_page":"36","last_page":"43"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.6460838913917542},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6432822346687317},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6432349681854248},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.616256058216095},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5949504971504211},{"id":"https://openalex.org/keywords/iddq-testing","display_name":"Iddq testing","score":0.5675902366638184},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5551024675369263},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.4488247036933899},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.42686957120895386},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4220942258834839},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4174294173717499},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3148648738861084},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3122125267982483},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.23035067319869995}],"concepts":[{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.6460838913917542},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6432822346687317},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6432349681854248},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.616256058216095},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5949504971504211},{"id":"https://openalex.org/C206678392","wikidata":"https://www.wikidata.org/wiki/Q5987815","display_name":"Iddq testing","level":3,"score":0.5675902366638184},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5551024675369263},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.4488247036933899},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.42686957120895386},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4220942258834839},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4174294173717499},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3148648738861084},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3122125267982483},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.23035067319869995},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdt.2002.1033790","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2002.1033790","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.699999988079071,"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1496640557","https://openalex.org/W1569571376","https://openalex.org/W1880721252","https://openalex.org/W1909769229","https://openalex.org/W1913711070","https://openalex.org/W2074945051","https://openalex.org/W2130404536","https://openalex.org/W2147198689","https://openalex.org/W2150526221","https://openalex.org/W2151244242","https://openalex.org/W2166777727","https://openalex.org/W2534824542","https://openalex.org/W2788930157","https://openalex.org/W3138957206","https://openalex.org/W4242819225","https://openalex.org/W6748708091"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W140691178","https://openalex.org/W3115966393","https://openalex.org/W3127857378","https://openalex.org/W2136187879","https://openalex.org/W2911152661","https://openalex.org/W3210903312","https://openalex.org/W2940351376","https://openalex.org/W2166386585","https://openalex.org/W2619662371"],"abstract_inverted_index":{"Barriers":[0],"to":[1,40],"technology":[2],"scaling,":[3],"such":[4],"as":[5],"leakage":[6,32],"and":[7,30,37],"parameter":[8],"variations,":[9],"challenge":[10],"the":[11],"effectiveness":[12],"of":[13,28],"current-based":[14],"test":[15,20],"techniques.":[16],"This":[17],"correlative":[18],"multiparameter":[19],"approach":[21],"improves":[22],"current":[23],"testing":[24],"sensitivity,":[25],"exploiting":[26],"dependencies":[27],"transistor":[29],"circuit":[31],"on":[33],"operating":[34],"frequency,":[35],"temperature,":[36],"body":[38],"bias":[39],"discriminate":[41],"fast":[42],"but":[43],"intrinsically":[44],"leaky":[45],"ICs":[46],"from":[47],"defective":[48],"ones.":[49]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
