{"id":"https://openalex.org/W2027657928","doi":"https://doi.org/10.1109/mdt.2002.1018137","title":"Automatic synthesis of communication controller hardware from protocol specifications","display_name":"Automatic synthesis of communication controller hardware from protocol specifications","publication_year":2002,"publication_date":"2002-07-01","ids":{"openalex":"https://openalex.org/W2027657928","doi":"https://doi.org/10.1109/mdt.2002.1018137","mag":"2027657928"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2002.1018137","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2002.1018137","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085354617","display_name":"Robert Siegmund","orcid":null},"institutions":[{"id":"https://openalex.org/I2610724","display_name":"Chemnitz University of Technology","ror":"https://ror.org/00a208s56","country_code":"DE","type":"education","lineage":["https://openalex.org/I2610724"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"R. Siegmund","raw_affiliation_strings":["Chemnitz University of Technology, Germany","Chemnitz University of Technology , Germany"],"affiliations":[{"raw_affiliation_string":"Chemnitz University of Technology, Germany","institution_ids":["https://openalex.org/I2610724"]},{"raw_affiliation_string":"Chemnitz University of Technology , Germany","institution_ids":["https://openalex.org/I2610724"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040088416","display_name":"Dietmar M\u00fcller","orcid":null},"institutions":[{"id":"https://openalex.org/I2610724","display_name":"Chemnitz University of Technology","ror":"https://ror.org/00a208s56","country_code":"DE","type":"education","lineage":["https://openalex.org/I2610724"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"D. Muller","raw_affiliation_strings":["Chemnitz University of Technology, Germany","Chemnitz University of Technology , Germany"],"affiliations":[{"raw_affiliation_string":"Chemnitz University of Technology, Germany","institution_ids":["https://openalex.org/I2610724"]},{"raw_affiliation_string":"Chemnitz University of Technology , Germany","institution_ids":["https://openalex.org/I2610724"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5085354617"],"corresponding_institution_ids":["https://openalex.org/I2610724"],"apc_list":null,"apc_paid":null,"fwci":1.3551,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.79522268,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"19","issue":"4","first_page":"84","last_page":"95"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7482646703720093},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.69169020652771},{"id":"https://openalex.org/keywords/communications-protocol","display_name":"Communications protocol","score":0.6060813665390015},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5891762971878052},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5163111090660095},{"id":"https://openalex.org/keywords/synchronous-serial-communication","display_name":"Synchronous serial communication","score":0.4882843494415283},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.43571722507476807},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.4135602116584778},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.3970426321029663},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3731679618358612},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14748594164848328},{"id":"https://openalex.org/keywords/serial-port","display_name":"Serial port","score":0.1425512135028839},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.13602077960968018},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10333758592605591}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7482646703720093},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.69169020652771},{"id":"https://openalex.org/C12269588","wikidata":"https://www.wikidata.org/wiki/Q132364","display_name":"Communications protocol","level":2,"score":0.6060813665390015},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5891762971878052},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5163111090660095},{"id":"https://openalex.org/C155787647","wikidata":"https://www.wikidata.org/wiki/Q2375695","display_name":"Synchronous serial communication","level":4,"score":0.4882843494415283},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.43571722507476807},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.4135602116584778},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.3970426321029663},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3731679618358612},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14748594164848328},{"id":"https://openalex.org/C102349902","wikidata":"https://www.wikidata.org/wiki/Q385390","display_name":"Serial port","level":3,"score":0.1425512135028839},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.13602077960968018},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10333758592605591},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdt.2002.1018137","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2002.1018137","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1498455513","https://openalex.org/W1560082788","https://openalex.org/W1987557508","https://openalex.org/W2000667158","https://openalex.org/W2002089154","https://openalex.org/W2074543488","https://openalex.org/W2081938726","https://openalex.org/W2100519472","https://openalex.org/W2109821573","https://openalex.org/W2109957573","https://openalex.org/W2160642395","https://openalex.org/W2160707486","https://openalex.org/W4232281993","https://openalex.org/W4248688512","https://openalex.org/W4249482284","https://openalex.org/W4253103663","https://openalex.org/W4302339081"],"related_works":["https://openalex.org/W2367164614","https://openalex.org/W2376526689","https://openalex.org/W2373957197","https://openalex.org/W2366355474","https://openalex.org/W2354541515","https://openalex.org/W2359227508","https://openalex.org/W2386154964","https://openalex.org/W2386525573","https://openalex.org/W2355666617","https://openalex.org/W2379301077"],"abstract_inverted_index":{"Controllers":[0],"for":[1,28,37],"serial":[2],"protocols":[3],"are":[4],"control-oriented":[5],"designs":[6],"that":[7,88],"include":[8],"complex":[9],"state":[10],"machines.":[11],"Manually":[12],"designing":[13],"protocol":[14,76,101],"controllers":[15,96],"is":[16],"thus":[17],"tedious,":[18],"error":[19],"prone,":[20],"and":[21,94],"time-consuming.":[22],"We":[23],"present":[24],"a":[25,51,61,69,74],"new":[26],"methodology":[27,46],"the":[29,56,65,90,99],"efficient":[30],"design":[31],"of":[32,55,64],"communication":[33,71],"controller":[34,48],"hardware":[35,49],"suited":[36],"(but":[38],"not":[39,80],"limited":[40],"to)":[41],"complex,":[42],"bit-serial":[43],"protocols.":[44],"Our":[45],"synthesizes":[47,68],"from":[50,73],"formal":[52],"high-level":[53],"specification":[54],"protocol.":[57],"In":[58],"this":[59],"approach,":[60],"single":[62,75],"run":[63],"synthesis":[66],"algorithm":[67],"complete":[70],"architecture":[72],"specification.":[77,102],"The":[78],"method":[79],"only":[81],"reduces":[82],"modeling":[83],"effort":[84],"but":[85],"also":[86],"ensures":[87],"both":[89],"interacting":[91],"transaction":[92],"producer":[93],"consumer":[95],"conform":[97],"to":[98],"initial":[100]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}