{"id":"https://openalex.org/W2086848907","doi":"https://doi.org/10.1109/mdt.2002.1018136","title":"Behavioral simulation of fractional-N frequency synthesizers and other PLL circuits","display_name":"Behavioral simulation of fractional-N frequency synthesizers and other PLL circuits","publication_year":2002,"publication_date":"2002-07-01","ids":{"openalex":"https://openalex.org/W2086848907","doi":"https://doi.org/10.1109/mdt.2002.1018136","mag":"2086848907"},"language":"en","primary_location":{"id":"doi:10.1109/mdt.2002.1018136","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2002.1018136","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054497844","display_name":"Michael H. Perrott","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M.H. Perrott","raw_affiliation_strings":["Electrical Engineering and Computer Science Department, Massachusetts Institute of Technology, Cambridge, MA","[Electrical Engineering and Computer Science Department, Massachusetts Institute of Technology, Cambridge, MA]"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Science Department, Massachusetts Institute of Technology, Cambridge, MA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"[Electrical Engineering and Computer Science Department, Massachusetts Institute of Technology, Cambridge, MA]","institution_ids":["https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5054497844"],"corresponding_institution_ids":["https://openalex.org/I63966007"],"apc_list":null,"apc_paid":null,"fwci":1.3578,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.80729665,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"19","issue":"4","first_page":"74","last_page":"83"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9797000288963318,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11247","display_name":"Plant nutrient uptake and metabolism","score":0.9577999711036682,"subfield":{"id":"https://openalex.org/subfields/1110","display_name":"Plant Science"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7980710864067078},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6883665323257446},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6499336957931519},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6059199571609497},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.5725250840187073},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5629284381866455},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36177289485931396},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.2911503314971924},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2597469687461853},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22229266166687012},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17299208045005798},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15085071325302124}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7980710864067078},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6883665323257446},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6499336957931519},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6059199571609497},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.5725250840187073},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5629284381866455},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36177289485931396},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.2911503314971924},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2597469687461853},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22229266166687012},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17299208045005798},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15085071325302124},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdt.2002.1018136","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdt.2002.1018136","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1495851026","https://openalex.org/W1580873078","https://openalex.org/W1594101521","https://openalex.org/W1766888123","https://openalex.org/W1998284495","https://openalex.org/W2103018069","https://openalex.org/W2107208989","https://openalex.org/W2124729073","https://openalex.org/W2124793342","https://openalex.org/W2125980634","https://openalex.org/W2167284852","https://openalex.org/W2171035445","https://openalex.org/W2476112607","https://openalex.org/W2478884216","https://openalex.org/W2490904451","https://openalex.org/W2994342738","https://openalex.org/W4246804698"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W4360861688","https://openalex.org/W3134930219","https://openalex.org/W984417604","https://openalex.org/W2967785526","https://openalex.org/W1761969858","https://openalex.org/W2391854357","https://openalex.org/W4238487776","https://openalex.org/W3114194214","https://openalex.org/W2132512458"],"abstract_inverted_index":{"Two":[0],"techniques":[1,21,36],"are":[2,37],"presented":[3],"that":[4],"allow":[5],"fast":[6],"and":[7,30,50],"accurate":[8],"simulation":[9,24,42],"of":[10,19,43],"fractional-N":[11],"synthesizers.":[12],"A":[13],"uniform":[14],"time":[15],"step":[16],"allows":[17],"implementation":[18],"these":[20],"in":[22],"various":[23],"frameworks,":[25],"such":[26,47],"as":[27,48],"Verilog,":[28],"Matlab,":[29],"C":[31],"or":[32],"C++":[33],"programs.":[34],"The":[35],"also":[38],"applicable":[39],"to":[40],"the":[41],"other":[44],"PLL":[45],"systems,":[46],"clock":[49],"data":[51],"recovery":[52],"circuits.":[53]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
