{"id":"https://openalex.org/W7133293993","doi":"https://doi.org/10.1109/mdat.2026.3670060","title":"Bridging RTL and Assertion Generation With Large Language Models","display_name":"Bridging RTL and Assertion Generation With Large Language Models","publication_year":2026,"publication_date":"2026-03-03","ids":{"openalex":"https://openalex.org/W7133293993","doi":"https://doi.org/10.1109/mdat.2026.3670060"},"language":null,"primary_location":{"id":"doi:10.1109/mdat.2026.3670060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2026.3670060","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5118659676","display_name":"Jayanth Thangellamudi","orcid":null},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jayanth Thangellamudi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA, USA"],"raw_orcid":"https://orcid.org/0009-0007-1319-9601","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA, USA","institution_ids":["https://openalex.org/I162714631"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047725314","display_name":"Sai Manoj Pudukotai Dinakarrao","orcid":"https://orcid.org/0000-0002-4417-2387"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sai Manoj Pudukotai Dinakarrao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA, USA"],"raw_orcid":"https://orcid.org/0000-0002-4417-2387","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA, USA","institution_ids":["https://openalex.org/I162714631"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162714631"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21764677,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"43","issue":"3","first_page":"5","last_page":"13"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10181","display_name":"Natural Language Processing Techniques","score":0.49810001254081726,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10181","display_name":"Natural Language Processing Techniques","score":0.49810001254081726,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10028","display_name":"Topic Modeling","score":0.2847000062465668,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10201","display_name":"Speech Recognition and Synthesis","score":0.03009999915957451,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.8640000224113464},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.7269999980926514},{"id":"https://openalex.org/keywords/assertion","display_name":"Assertion","score":0.7106999754905701},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5325000286102295},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.4661000072956085},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4320000112056732},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.3921999931335449},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.3734999895095825},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.3666999936103821}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.8640000224113464},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8497999906539917},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.7473000288009644},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.7269999980926514},{"id":"https://openalex.org/C40422974","wikidata":"https://www.wikidata.org/wiki/Q741248","display_name":"Assertion","level":2,"score":0.7106999754905701},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5325000286102295},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.4661000072956085},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4320000112056732},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.3921999931335449},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.3734999895095825},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.3666999936103821},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3513999879360199},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.30169999599456787},{"id":"https://openalex.org/C137293760","wikidata":"https://www.wikidata.org/wiki/Q3621696","display_name":"Language model","level":2,"score":0.2867000102996826},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2865000069141388},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.2818000018596649},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.27959999442100525},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.2736999988555908},{"id":"https://openalex.org/C60048249","wikidata":"https://www.wikidata.org/wiki/Q37437","display_name":"Syntax","level":2,"score":0.2639000117778778},{"id":"https://openalex.org/C179603123","wikidata":"https://www.wikidata.org/wiki/Q1941921","display_name":"Modeling language","level":3,"score":0.2619999945163727},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2614000141620636},{"id":"https://openalex.org/C61423126","wikidata":"https://www.wikidata.org/wiki/Q187432","display_name":"Scripting language","level":2,"score":0.2578999996185303},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.25600001215934753},{"id":"https://openalex.org/C98183937","wikidata":"https://www.wikidata.org/wiki/Q2112188","display_name":"Program analysis","level":2,"score":0.25519999861717224},{"id":"https://openalex.org/C152752567","wikidata":"https://www.wikidata.org/wiki/Q116877","display_name":"Code refactoring","level":3,"score":0.2524999976158142},{"id":"https://openalex.org/C48859967","wikidata":"https://www.wikidata.org/wiki/Q6486712","display_name":"Language construct","level":2,"score":0.2500999867916107}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2026.3670060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2026.3670060","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2378873228","display_name":"Collaborative Research: EAGER: IC-Cloak: Integrated Circuit Cloaking against Reverse Engineering","funder_award_id":"2213404","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W4392405447","https://openalex.org/W4393145520","https://openalex.org/W4402835956","https://openalex.org/W4403023462","https://openalex.org/W4411120222"],"related_works":[],"abstract_inverted_index":{"The":[0],"rapid":[1],"increase":[2],"in":[3,115,143],"hardware":[4,43,69],"design":[5,147],"complexity":[6],"has":[7],"made":[8],"manual":[9,95],"verification":[10,99],"processes":[11],"inefficient,":[12],"error-prone,":[13],"and":[14,75,97,111,134,148],"unscalable,":[15],"underscoring":[16],"the":[17,38,125],"need":[18],"for":[19,42,52,67],"robust":[20],"automated":[21,68],"validation.":[22],"Emerging":[23],"large":[24],"language":[25],"models":[26,130],"(LLMs)":[27],"excel":[28],"at":[29],"code":[30,74,116],"generation,":[31,117],"however":[32],"their":[33],"general":[34],"training":[35],"often":[36],"lacks":[37],"domain-specific":[39,102],"expertise":[40],"required":[41],"description":[44],"languages":[45],"(HDLs)":[46],"like":[47],"Verilog,":[48],"which":[49],"is":[50],"essential":[51],"reliable":[53],"automation.":[54],"To":[55],"address":[56,84],"these":[57,85],"challenges,":[58],"we":[59],"propose":[60],"a":[61,140],"dual-stage":[62],"framework":[63,89],"that":[64,83],"fine-tunes":[65],"LLaMA2-7B":[66],"validation,":[70],"specifically":[71],"targeting":[72],"Verilog":[73],"SystemVerilog":[76],"assertion":[77,119],"(SVA)":[78],"generation.":[79],"Unlike":[80],"existing":[81],"approaches":[82],"tasks":[86],"separately,":[87],"our":[88,104],"unifies":[90],"them":[91],"to":[92],"significantly":[93],"reduce":[94],"intervention":[96],"enhance":[98],"robustness.":[100],"Through":[101],"training,":[103],"method":[105],"achieves":[106],"high":[107],"syntactic":[108],"correctness":[109,123],"92%":[110],"functional":[112],"accuracy":[113],"93%":[114],"while":[118],"generation":[120],"reaches":[121],"88%":[122],"on":[124],"RTLLM":[126],"benchmarks,":[127],"outperforming":[128],"state-of-the-art":[129],"such":[131],"as":[132],"GPT-4":[133],"StarCoder.":[135],"This":[136],"comprehensive":[137],"approach":[138],"marks":[139],"transformative":[141],"advancement":[142],"AI-driven":[144],"digital":[145],"circuit":[146],"verification.":[149]},"counts_by_year":[],"updated_date":"2026-08-12T21:12:35.861297","created_date":"2026-03-04T00:00:00"}