{"id":"https://openalex.org/W4366678158","doi":"https://doi.org/10.1109/mdat.2023.3269391","title":"NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links","display_name":"NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links","publication_year":2023,"publication_date":"2023-04-21","ids":{"openalex":"https://openalex.org/W4366678158","doi":"https://doi.org/10.1109/mdat.2023.3269391"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2023.3269391","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/mdat.2023.3269391","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043179142","display_name":"Mahmut Yilmaz","orcid":"https://orcid.org/0000-0002-4522-7028"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mahmut Yilmaz","raw_affiliation_strings":["NVIDIA Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041362633","display_name":"Pavan Kumar Datla Jagannadha","orcid":"https://orcid.org/0009-0007-7962-3727"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pavan Kumar Datla Jagannadha","raw_affiliation_strings":["NVIDIA Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038085485","display_name":"Kaushik Narayanun","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Narayanun","raw_affiliation_strings":["NVIDIA Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009749203","display_name":"Shantanu Sarangi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shantanu Sarangi","raw_affiliation_strings":["NVIDIA Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029748815","display_name":"Francisco da Silva","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Francisco da Silva","raw_affiliation_strings":["NVIDIA Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014777061","display_name":"Joe Sarmiento","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joe Sarmiento","raw_affiliation_strings":["NVIDIA Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5043179142"],"corresponding_institution_ids":["https://openalex.org/I4210127875"],"apc_list":null,"apc_paid":null,"fwci":0.1339,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.40418595,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"40","issue":"4","first_page":"25","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10624","display_name":"Silicon and Solar Cell Technologies","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.991100013256073,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pci-express","display_name":"PCI Express","score":0.9091126322746277},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6654706001281738},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5470004677772522},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5392664074897766},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.49980592727661133},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.48074984550476074},{"id":"https://openalex.org/keywords/mechanism","display_name":"Mechanism (biology)","score":0.42831653356552124},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3891112208366394},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3823256492614746},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33049294352531433},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3200386166572571}],"concepts":[{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.9091126322746277},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6654706001281738},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5470004677772522},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5392664074897766},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.49980592727661133},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.48074984550476074},{"id":"https://openalex.org/C89611455","wikidata":"https://www.wikidata.org/wiki/Q6804646","display_name":"Mechanism (biology)","level":2,"score":0.42831653356552124},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3891112208366394},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3823256492614746},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33049294352531433},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3200386166572571},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2023.3269391","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/mdat.2023.3269391","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2051503284","https://openalex.org/W2570739159","https://openalex.org/W2958469817","https://openalex.org/W4246741113","https://openalex.org/W4282978145","https://openalex.org/W6731495857"],"related_works":["https://openalex.org/W4385894176","https://openalex.org/W2347371119","https://openalex.org/W2612768808","https://openalex.org/W3131402800","https://openalex.org/W2593071546","https://openalex.org/W1564576805","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882"],"abstract_inverted_index":{"The":[0,65],"Mechanism":[1],"to":[2,14,61],"Access":[3],"Test-Data":[4],"over":[5],"High-Speed":[6],"Link":[7],"(MATHS)":[8],"provides":[9],"a":[10],"high-throughput":[11],"PCIe-based":[12],"system":[13,22,35,66],"structurally":[15],"test":[16,42,62],"system-on-chips":[17],"(SoCs)":[18],"at":[19,33],"wafer":[20],"and":[21,37,51,54,84],"levels.":[23],"With":[24],"this":[25],"system,":[26],"the":[27,34,38,47,63],"SoC":[28],"can":[29,58],"be":[30,59],"directly":[31],"tested":[32],"level":[36],"reliance":[39],"on":[40,69],"expensive":[41],"equipment.":[43],"Since":[44],"MATHS":[45],"simplifies":[46],"necessary":[48],"ATE":[49],"architecture":[50],"design,":[52],"smaller":[53],"lower":[55],"cost":[56],"testers":[57],"employed":[60],"SoC.":[64],"is":[67],"based":[68],"PCIe":[70],"standards,":[71],"making":[72],"it":[73],"highly":[74],"portable":[75],"across":[76],"all":[77],"platforms,":[78],"including":[79],"ATE,":[80],"system-level":[81],"test,":[82],"board,":[83],"in-field":[85],"testing.":[86]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-12-23T23:11:35.936235","created_date":"2025-10-10T00:00:00"}
