{"id":"https://openalex.org/W4206839573","doi":"https://doi.org/10.1109/mdat.2021.3133378","title":"On-Chip Jitter Learning for PLL","display_name":"On-Chip Jitter Learning for PLL","publication_year":2021,"publication_date":"2021-12-06","ids":{"openalex":"https://openalex.org/W4206839573","doi":"https://doi.org/10.1109/mdat.2021.3133378"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2021.3133378","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2021.3133378","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100743982","display_name":"Wei-Hao Chen","orcid":"https://orcid.org/0000-0002-1337-0137"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Hao Chen","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu City, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu City, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085636078","display_name":"Shi\u2010Yu Huang","orcid":"https://orcid.org/0000-0002-3721-987X"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shi-Yu Huang","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu City, Taiwan"],"raw_orcid":"https://orcid.org/0000-0002-3721-987X","affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu City, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17586636,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"39","issue":"4","first_page":"58","last_page":"63"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9535310864448547},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.9323655366897583},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.6892753839492798},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6215038895606995},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5962244868278503},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5771637558937073},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5610929131507874},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.49846577644348145},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.49392229318618774},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4691084027290344},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4500636160373688},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42675361037254333},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41878026723861694},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2735435366630554},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20206326246261597},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10529515147209167},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07810059189796448}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9535310864448547},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.9323655366897583},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.6892753839492798},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6215038895606995},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5962244868278503},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5771637558937073},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5610929131507874},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.49846577644348145},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.49392229318618774},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4691084027290344},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4500636160373688},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42675361037254333},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41878026723861694},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2735435366630554},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20206326246261597},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10529515147209167},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07810059189796448},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2021.3133378","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2021.3133378","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2994856808","display_name":null,"funder_award_id":"109-2224-E-007-006","funder_id":"https://openalex.org/F4320322795","funder_display_name":"Ministry of Science and Technology, Taiwan"}],"funders":[{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2014849399","https://openalex.org/W2062819218","https://openalex.org/W2067333289","https://openalex.org/W2078267331","https://openalex.org/W2100452539","https://openalex.org/W2105386586","https://openalex.org/W2111679634","https://openalex.org/W2128037349","https://openalex.org/W2145873744","https://openalex.org/W2159971659","https://openalex.org/W2171035445","https://openalex.org/W3123493989","https://openalex.org/W6678817957"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W2104055211","https://openalex.org/W2498262093","https://openalex.org/W2139484866","https://openalex.org/W2188779191","https://openalex.org/W2967785526","https://openalex.org/W188830667","https://openalex.org/W1605914315","https://openalex.org/W4360861688","https://openalex.org/W1994021281"],"abstract_inverted_index":{"A":[0,53],"phase-locked":[1],"loop":[2],"(PLL)":[3],"is":[4,55],"a":[5,26,64],"fundamental":[6],"building":[7],"block":[8],"in":[9],"integrated":[10],"circuits":[11],"used":[12],"for":[13,31],"stable":[14],"on-chip":[15],"clock":[16,50],"signal":[17,51],"generation,":[18],"among":[19],"other":[20],"applications.":[21],"This":[22],"article":[23],"shows":[24],"how":[25],"PLL":[27],"can":[28],"be":[29,75],"augmented":[30],"online":[32],"learning":[33],"and":[34,82],"suppression":[35,72],"of":[36,41],"the":[37,42,59,71,79],"peak-to-peak":[38,60],"jitter,":[39],"one":[40],"key":[43],"characteristics":[44],"when":[45],"it":[46],"comes":[47],"to":[48,57,74],"high-speed":[49],"generation.":[52],"monitor":[54],"proposed":[56],"assess":[58],"jitter":[61],"followed":[62],"by":[63],"feedback":[65],"mechanism":[66],"that":[67],"automatically":[68],"decides":[69],"on":[70,78],"level":[73],"applied":[76],"depending":[77],"process,":[80],"voltage,":[81],"temperature":[83],"conditions.":[84]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
