{"id":"https://openalex.org/W3001665573","doi":"https://doi.org/10.1109/mdat.2020.2968255","title":"Testing of Prebond Through Silicon Vias","display_name":"Testing of Prebond Through Silicon Vias","publication_year":2020,"publication_date":"2020-01-20","ids":{"openalex":"https://openalex.org/W3001665573","doi":"https://doi.org/10.1109/mdat.2020.2968255","mag":"3001665573"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2020.2968255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2020.2968255","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100657679","display_name":"Sourav Das","orcid":"https://orcid.org/0000-0002-7404-8133"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sourav Das","raw_affiliation_strings":["Intel Corporation, Santa Clara"],"raw_orcid":"https://orcid.org/0000-0002-7404-8133","affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036373418","display_name":"Fei Su","orcid":"https://orcid.org/0000-0002-2585-6564"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fei Su","raw_affiliation_strings":["Intel Corporation, Santa Clara"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102184443","display_name":"Sreejit Chakravarty","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sreejit Chakravarty","raw_affiliation_strings":["Intel Corporation, Santa Clara"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.2019,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.4756141,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"37","issue":"4","first_page":"27","last_page":"34"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.6546493768692017},{"id":"https://openalex.org/keywords/stack","display_name":"Stack (abstract data type)","score":0.6067615151405334},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5941252112388611},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.5779013633728027},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4872788190841675},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.48425957560539246},{"id":"https://openalex.org/keywords/manufacturing-process","display_name":"Manufacturing process","score":0.4549819827079773},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3395140767097473},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.30393755435943604},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.17229068279266357}],"concepts":[{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.6546493768692017},{"id":"https://openalex.org/C9395851","wikidata":"https://www.wikidata.org/wiki/Q177929","display_name":"Stack (abstract data type)","level":2,"score":0.6067615151405334},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5941252112388611},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.5779013633728027},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4872788190841675},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.48425957560539246},{"id":"https://openalex.org/C2987875673","wikidata":"https://www.wikidata.org/wiki/Q187939","display_name":"Manufacturing process","level":2,"score":0.4549819827079773},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3395140767097473},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.30393755435943604},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.17229068279266357},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2020.2968255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2020.2968255","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1535622131","https://openalex.org/W1981312567","https://openalex.org/W2124433198","https://openalex.org/W2142339929","https://openalex.org/W2155707315","https://openalex.org/W2188487610","https://openalex.org/W2913388696","https://openalex.org/W6632127416"],"related_works":["https://openalex.org/W4289538008","https://openalex.org/W3186427148","https://openalex.org/W2138282914","https://openalex.org/W2065850627","https://openalex.org/W2017012638","https://openalex.org/W1966793535","https://openalex.org/W2071885361","https://openalex.org/W1964447062","https://openalex.org/W1978219043","https://openalex.org/W2088265144"],"abstract_inverted_index":{"Testing":[0],"of":[1],"the":[2],"interconnects":[3],"in":[4],"a":[5,9,17],"3-D":[6],"stack":[7],"is":[8],"complex":[10],"and":[11,26],"expensive":[12],"process.":[13],"The":[14],"authors":[15],"propose":[16],"method":[18],"using":[19],"prebond":[20],"testing":[21],"to":[22],"reduce":[23],"manufacturing":[24],"cost":[25],"improve":[27],"overall":[28],"yield.-Vivek":[29],"Chickermane,":[30],"Cadence":[31],"Design":[32],"Systems.":[33]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
