{"id":"https://openalex.org/W2791475545","doi":"https://doi.org/10.1109/mdat.2018.2799800","title":"ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed- Signal Integrated Circuits","display_name":"ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed- Signal Integrated Circuits","publication_year":2018,"publication_date":"2018-01-30","ids":{"openalex":"https://openalex.org/W2791475545","doi":"https://doi.org/10.1109/mdat.2018.2799800","mag":"2791475545"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2018.2799800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2018.2799800","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017481892","display_name":"Anthony Coyette","orcid":"https://orcid.org/0000-0002-3221-4578"},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":true,"raw_author_name":"Anthony Coyette","raw_affiliation_strings":["Department of Electrical Engineering, KU Leuven, Leuven, Belgium"],"raw_orcid":"https://orcid.org/0000-0002-3221-4578","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KU Leuven, Leuven, Belgium","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005068808","display_name":"Baris Esen","orcid":"https://orcid.org/0000-0002-5540-4374"},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Baris Esen","raw_affiliation_strings":["KU Leuven"],"raw_orcid":"https://orcid.org/0000-0002-5540-4374","affiliations":[{"raw_affiliation_string":"KU Leuven","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066688200","display_name":"Nektar Xama","orcid":"https://orcid.org/0000-0001-5286-1759"},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Nektar Xama","raw_affiliation_strings":["KU Leuven"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KU Leuven","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029270525","display_name":"Georges Gielen","orcid":"https://orcid.org/0000-0002-4061-9428"},"institutions":[{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Georges Gielen","raw_affiliation_strings":["KU Leuven"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KU Leuven","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028691975","display_name":"Wim Dobbelaere","orcid":null},"institutions":[{"id":"https://openalex.org/I4210110772","display_name":"ON Semiconductor (Belgium)","ror":"https://ror.org/0212gej90","country_code":"BE","type":"company","lineage":["https://openalex.org/I100625452","https://openalex.org/I4210110772"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Wim Dobbelaere","raw_affiliation_strings":["ON Semiconductor Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ON Semiconductor Belgium","institution_ids":["https://openalex.org/I4210110772"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062808173","display_name":"Ronny Vanhooren","orcid":null},"institutions":[{"id":"https://openalex.org/I4210110772","display_name":"ON Semiconductor (Belgium)","ror":"https://ror.org/0212gej90","country_code":"BE","type":"company","lineage":["https://openalex.org/I100625452","https://openalex.org/I4210110772"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Ronny Vanhooren","raw_affiliation_strings":["ON Semiconductor Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ON Semiconductor Belgium","institution_ids":["https://openalex.org/I4210110772"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5017481892"],"corresponding_institution_ids":["https://openalex.org/I99464096"],"apc_list":null,"apc_paid":null,"fwci":0.7882,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.68601431,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"35","issue":"3","first_page":"24","last_page":"30"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6968600153923035},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.6259772777557373},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.6202608942985535},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.6075758337974548},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5998361110687256},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5600505471229553},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.5314029455184937},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.521550178527832},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.49697616696357727},{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"Automatic test equipment","score":0.4520438313484192},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36917558312416077},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34751808643341064},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3257940709590912},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20455563068389893},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14635953307151794},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.1393066644668579}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6968600153923035},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.6259772777557373},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.6202608942985535},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.6075758337974548},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5998361110687256},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5600505471229553},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.5314029455184937},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.521550178527832},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.49697616696357727},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.4520438313484192},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36917558312416077},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34751808643341064},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3257940709590912},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20455563068389893},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14635953307151794},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.1393066644668579},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/mdat.2018.2799800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2018.2799800","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"},{"id":"pmh:oai:lirias2repo.kuleuven.be:20.500.12942/738726","is_oa":false,"landing_page_url":"https://lirias.kuleuven.be/handle/20.500.12942/738726","pdf_url":null,"source":{"id":"https://openalex.org/S4306401954","display_name":"Lirias (KU Leuven)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I99464096","host_organization_name":"KU Leuven","host_organization_lineage":["https://openalex.org/I99464096"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"Ieee Design & Test, vol. 35 (3), Art.No. 3, (24-30)","raw_type":"info:eu-repo/semantics/acceptedVersion"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1481383401","https://openalex.org/W1486817281","https://openalex.org/W1555979208","https://openalex.org/W1901574727","https://openalex.org/W2024387243","https://openalex.org/W2116967920","https://openalex.org/W2129444872","https://openalex.org/W2133952565","https://openalex.org/W2189035499","https://openalex.org/W2514345360","https://openalex.org/W2532291985","https://openalex.org/W2570705108","https://openalex.org/W4250463917","https://openalex.org/W4254936889"],"related_works":["https://openalex.org/W2157212570","https://openalex.org/W2543176856","https://openalex.org/W2031235560","https://openalex.org/W2764440971","https://openalex.org/W1897203488","https://openalex.org/W2616892825","https://openalex.org/W1837475237","https://openalex.org/W1901574727","https://openalex.org/W2624668974","https://openalex.org/W3088373974"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,25],"integrated":[4],"workflow":[5],"for":[6],"design-for-test":[7],"and":[8,23],"test":[9,22,30],"signal":[10],"generation":[11,28],"of":[12,29],"mixed-signal":[13],"circuits.":[14],"The":[15],"DfT":[16],"phase":[17],"pre-partitions":[18],"the":[19],"core":[20],"under":[21],"allows":[24],"efficient":[26],"automatic":[27],"signals.":[31]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
