{"id":"https://openalex.org/W2524658815","doi":"https://doi.org/10.1109/mdat.2016.2562060","title":"Test Cost Reduction Methodology for In-FO Wafer-Level Chip-Scale Package","display_name":"Test Cost Reduction Methodology for In-FO Wafer-Level Chip-Scale Package","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2524658815","doi":"https://doi.org/10.1109/mdat.2016.2562060","mag":"2524658815"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2016.2562060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2016.2562060","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100757027","display_name":"Kai\u2010Li Wang","orcid":"https://orcid.org/0000-0002-8546-6824"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kai-Li Wang","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001799301","display_name":"Bing-Yang Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Bing-Yang Lin","raw_affiliation_strings":["National Tsing Hua University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing Hua University","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075548524","display_name":"Cheng\u2010Wen Wu","orcid":"https://orcid.org/0000-0001-8614-7908"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-Wen Wu","raw_affiliation_strings":["National Tsing Hua University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing Hua University","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049439798","display_name":"Mincent Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mincent Lee","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company, Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company, Ltd","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100353582","display_name":"Hao Chen","orcid":"https://orcid.org/0000-0002-6995-0288"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hao Chen","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company, Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company, Ltd","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103174920","display_name":"Hung\u2010Chih Lin","orcid":"https://orcid.org/0000-0002-8111-8371"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Chih Lin","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company, Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company, Ltd","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113691309","display_name":"Ching-Nen Peng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Nen Peng","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company, Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company, Ltd","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086368713","display_name":"Min-Jer Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Min-Jer Wang","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company, Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company, Ltd","institution_ids":["https://openalex.org/I4210120917"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5346,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.70617398,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chip-scale-package","display_name":"Chip-scale package","score":0.908892035484314},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.6066374778747559},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5987319946289062},{"id":"https://openalex.org/keywords/cost-reduction","display_name":"Cost reduction","score":0.5957559943199158},{"id":"https://openalex.org/keywords/wafer-scale-integration","display_name":"Wafer-scale integration","score":0.5835881233215332},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5657340884208679},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.555879533290863},{"id":"https://openalex.org/keywords/scale","display_name":"Scale (ratio)","score":0.5304638147354126},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5187009572982788},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5118200182914734},{"id":"https://openalex.org/keywords/wafer-level-packaging","display_name":"Wafer-level packaging","score":0.4695501923561096},{"id":"https://openalex.org/keywords/manufacturing-engineering","display_name":"Manufacturing engineering","score":0.3601248264312744},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29249483346939087},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15967780351638794},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.10260900855064392},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06991907954216003},{"id":"https://openalex.org/keywords/business","display_name":"Business","score":0.054206520318984985}],"concepts":[{"id":"https://openalex.org/C126233035","wikidata":"https://www.wikidata.org/wiki/Q5101572","display_name":"Chip-scale package","level":3,"score":0.908892035484314},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.6066374778747559},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5987319946289062},{"id":"https://openalex.org/C2778820799","wikidata":"https://www.wikidata.org/wiki/Q3454688","display_name":"Cost reduction","level":2,"score":0.5957559943199158},{"id":"https://openalex.org/C2778638305","wikidata":"https://www.wikidata.org/wiki/Q7406100","display_name":"Wafer-scale integration","level":3,"score":0.5835881233215332},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5657340884208679},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.555879533290863},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.5304638147354126},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5187009572982788},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5118200182914734},{"id":"https://openalex.org/C2780288131","wikidata":"https://www.wikidata.org/wiki/Q4017648","display_name":"Wafer-level packaging","level":3,"score":0.4695501923561096},{"id":"https://openalex.org/C117671659","wikidata":"https://www.wikidata.org/wiki/Q11049265","display_name":"Manufacturing engineering","level":1,"score":0.3601248264312744},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29249483346939087},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15967780351638794},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.10260900855064392},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06991907954216003},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.054206520318984985},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2016.2562060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2016.2562060","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6100000143051147,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W192757576","https://openalex.org/W1988399408","https://openalex.org/W1998432272","https://openalex.org/W2038020452","https://openalex.org/W2052075243","https://openalex.org/W2107118367","https://openalex.org/W2107304970","https://openalex.org/W2162968317","https://openalex.org/W2163755032","https://openalex.org/W2318697556","https://openalex.org/W3148440458","https://openalex.org/W4250657101","https://openalex.org/W6659778318"],"related_works":["https://openalex.org/W2156194080","https://openalex.org/W2795850397","https://openalex.org/W2146366317","https://openalex.org/W2970498257","https://openalex.org/W2041316527","https://openalex.org/W4200597737","https://openalex.org/W2136374712","https://openalex.org/W3146796940","https://openalex.org/W2153633039","https://openalex.org/W3022215011"],"abstract_inverted_index":{"Editor's":[0],"note:":[1],"To":[2],"reduce":[3],"the":[4,11,22,29,44,51,57],"manufacturing":[5],"cost":[6,33,47],"of":[7,21],"heterogeneous":[8],"3-D":[9],"integration,":[10],"Integrated":[12],"Fan-Out":[13],"Wafer-Level":[14],"Chip-Scale":[15],"Packaging":[16],"(InFO":[17],"WLCSP)":[18],"is":[19],"one":[20],"emerging":[23],"packaging":[24],"technologies.":[25],"In":[26],"this":[27],"article,":[28],"authors":[30],"propose":[31],"a":[32],"model":[34],"for":[35,42,55],"InFO":[36],"WLCSP,":[37],"which":[38],"can":[39],"be":[40],"used":[41],"analyzing":[43],"total":[45],"test":[46,52,58],"with":[48],"respect":[49],"to":[50],"configuration":[53,59],"and":[54,60],"optimizing":[56],"procedure.":[61]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}