{"id":"https://openalex.org/W2343526791","doi":"https://doi.org/10.1109/mdat.2015.2497322","title":"FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for &lt;sc&gt;nand&lt;/sc&gt; Flash Memories","display_name":"FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for &lt;sc&gt;nand&lt;/sc&gt; Flash Memories","publication_year":2015,"publication_date":"2015-11-03","ids":{"openalex":"https://openalex.org/W2343526791","doi":"https://doi.org/10.1109/mdat.2015.2497322","mag":"2343526791"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2015.2497322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2015.2497322","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066290481","display_name":"Syed Azhar Ali Zaidi","orcid":"https://orcid.org/0000-0001-8535-4905"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Syed Azhar Ali Zaidi","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Italy"],"raw_orcid":"https://orcid.org/0000-0001-8535-4905","affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046579275","display_name":"Abuduwaili Tuoheti","orcid":"https://orcid.org/0000-0003-0647-2212"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Abuduwaili Tuoheti","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026016005","display_name":"Maurizio Martina","orcid":"https://orcid.org/0000-0002-3069-0319"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Maurizio Martina","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074150684","display_name":"Guido Masera","orcid":"https://orcid.org/0000-0003-2238-9443"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Guido Masera","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.21564722,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"33","issue":"6","first_page":"77","last_page":"84"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/low-density-parity-check-code","display_name":"Low-density parity-check code","score":0.8454501628875732},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.7214918732643127},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7207615375518799},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.7084625959396362},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6159100532531738},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5449551343917847},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4898698031902313},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.4572680592536926},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3157743215560913},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.25456470251083374},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.18536511063575745},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1564684510231018},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11478874087333679},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08083707094192505}],"concepts":[{"id":"https://openalex.org/C67692717","wikidata":"https://www.wikidata.org/wiki/Q187444","display_name":"Low-density parity-check code","level":3,"score":0.8454501628875732},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7214918732643127},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7207615375518799},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.7084625959396362},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6159100532531738},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5449551343917847},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4898698031902313},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.4572680592536926},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3157743215560913},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.25456470251083374},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.18536511063575745},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1564684510231018},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11478874087333679},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08083707094192505},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2015.2497322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2015.2497322","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1533401668","https://openalex.org/W1970010894","https://openalex.org/W1990436563","https://openalex.org/W2020893403","https://openalex.org/W2048185145","https://openalex.org/W2067501233","https://openalex.org/W2101227239","https://openalex.org/W2110984563","https://openalex.org/W2114869758","https://openalex.org/W2115165154","https://openalex.org/W2179360174","https://openalex.org/W6631966399"],"related_works":["https://openalex.org/W1509155667","https://openalex.org/W2518118925","https://openalex.org/W2054139911","https://openalex.org/W1577524679","https://openalex.org/W3208151864","https://openalex.org/W2369836424","https://openalex.org/W2386432552","https://openalex.org/W4230869547","https://openalex.org/W2355887979","https://openalex.org/W4285309357"],"abstract_inverted_index":{"In":[0],"this":[1],"article,":[2],"the":[3,11],"authors":[4],"implement":[5],"an":[6],"FPGA":[7],"simulator":[8],"that":[9],"accelerates":[10],"performance":[12],"evaluation":[13],"of":[14],"very":[15],"long":[16],"QC-LDPC":[17],"codes,":[18],"and":[19],"present":[20],"a":[21],"novel":[22],"8-KB":[23],"LDPC":[24],"code":[25],"for":[26],"NAND":[27],"flash":[28],"memory":[29],"with":[30],"better":[31],"performance.":[32]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
