{"id":"https://openalex.org/W2334449737","doi":"https://doi.org/10.1109/mdat.2014.2381351","title":"Speeding Up Analog Integration and Test for Mixed-Signal SoCs [From the EIC]","display_name":"Speeding Up Analog Integration and Test for Mixed-Signal SoCs [From the EIC]","publication_year":2015,"publication_date":"2015-01-14","ids":{"openalex":"https://openalex.org/W2334449737","doi":"https://doi.org/10.1109/mdat.2014.2381351","mag":"2334449737"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2014.2381351","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mdat.2014.2381351","pdf_url":"https://ieeexplore.ieee.org/ielx7/6221038/7010066/07010113.pdf","source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://ieeexplore.ieee.org/ielx7/6221038/7010066/07010113.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062724257","display_name":"A. Ivanov","orcid":"https://orcid.org/0000-0002-0882-6750"},"institutions":[{"id":"https://openalex.org/I3132238960","display_name":"Institute of Electrical and Electronics Engineers","ror":"https://ror.org/01n002310","country_code":"US","type":"education","lineage":["https://openalex.org/I3132238960"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Andre Ivanov","raw_affiliation_strings":["IEEE Design & Test"],"affiliations":[{"raw_affiliation_string":"IEEE Design & Test","institution_ids":["https://openalex.org/I3132238960"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5062724257"],"corresponding_institution_ids":["https://openalex.org/I3132238960"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17049653,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"32","issue":"1","first_page":"4","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9675999879837036,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.8853528499603271},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.557199239730835},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.5419192910194397},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5232297778129578},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5179635286331177},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5140184164047241},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44317466020584106},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4183945059776306},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4044036269187927},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3975834250450134},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32278963923454285},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32135871052742004},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.1808357536792755},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.05783948302268982}],"concepts":[{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.8853528499603271},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.557199239730835},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.5419192910194397},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5232297778129578},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5179635286331177},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5140184164047241},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44317466020584106},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4183945059776306},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4044036269187927},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3975834250450134},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32278963923454285},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32135871052742004},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.1808357536792755},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.05783948302268982},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2014.2381351","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mdat.2014.2381351","pdf_url":"https://ieeexplore.ieee.org/ielx7/6221038/7010066/07010113.pdf","source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/mdat.2014.2381351","is_oa":true,"landing_page_url":"https://doi.org/10.1109/mdat.2014.2381351","pdf_url":"https://ieeexplore.ieee.org/ielx7/6221038/7010066/07010113.pdf","source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2334449737.pdf","grobid_xml":"https://content.openalex.org/works/W2334449737.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4242258007","https://openalex.org/W2155285526","https://openalex.org/W2394022884","https://openalex.org/W2071235072","https://openalex.org/W2185815555","https://openalex.org/W2375192119","https://openalex.org/W2053330176","https://openalex.org/W1981652693","https://openalex.org/W2076925294","https://openalex.org/W1862020018"],"abstract_inverted_index":{"Presents":[0],"an":[1],"editorial":[2],"that":[3],"addresses":[4],"the":[5,14],"main":[6],"topics":[7],"discussed":[8],"in":[9],"this":[10],"issue":[11],"focusing":[12],"on":[13],"complex":[15],"challenges":[16],"of":[17,22],"design,":[18],"verification,":[19],"and":[20,24,27],"test":[21],"analog":[23],"mixed-signal":[25],"circuits":[26],"SoCs.":[28]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}