{"id":"https://openalex.org/W2054635469","doi":"https://doi.org/10.1109/mdat.2013.2272693","title":"Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics","display_name":"Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics","publication_year":2013,"publication_date":"2013-07-10","ids":{"openalex":"https://openalex.org/W2054635469","doi":"https://doi.org/10.1109/mdat.2013.2272693","mag":"2054635469"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2013.2272693","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2013.2272693","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025451600","display_name":"Eddie Hung","orcid":"https://orcid.org/0000-0001-7670-116X"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Eddie Hung","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110217765","display_name":"Brad Quinton","orcid":null},"institutions":[{"id":"https://openalex.org/I1282770075","display_name":"Tektronix (United States)","ror":"https://ror.org/04kw5s604","country_code":"US","type":"company","lineage":["https://openalex.org/I1282770075"]},{"id":"https://openalex.org/I4210122675","display_name":"Tektronix (Canada)","ror":"https://ror.org/023mbkk92","country_code":"CA","type":"company","lineage":["https://openalex.org/I1282770075","https://openalex.org/I4210122675"]}],"countries":["CA","US"],"is_corresponding":false,"raw_author_name":"Brad Quinton","raw_affiliation_strings":["Embedded Instrumentation Group Tektronix, Inc., Vancouver, BC, Canada","Embedded Instrum. Group, Tektronix, Inc., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Embedded Instrumentation Group Tektronix, Inc., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I4210122675"]},{"raw_affiliation_string":"Embedded Instrum. Group, Tektronix, Inc., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I1282770075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J. E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.12175684,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"30","issue":"4","first_page":"8","last_page":"15"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5753142237663269},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3464566469192505},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1832588016986847}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5753142237663269},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3464566469192505},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1832588016986847}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2013.2272693","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2013.2272693","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1976150142","https://openalex.org/W2011645538","https://openalex.org/W2024436253","https://openalex.org/W2090692734","https://openalex.org/W2101700684","https://openalex.org/W2122146819","https://openalex.org/W2132894060","https://openalex.org/W2138383740","https://openalex.org/W2147524308","https://openalex.org/W2166862343","https://openalex.org/W2166930733","https://openalex.org/W6681649534"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2382290278","https://openalex.org/W2350741829","https://openalex.org/W3004735627","https://openalex.org/W2130043461","https://openalex.org/W2530322880"],"abstract_inverted_index":{"This":[0],"paper":[1],"discusses":[2],"the":[3,7],"current":[4],"state":[5],"of":[6],"art":[8],"in":[9,16],"measuring":[10],"validation":[11],"coverage":[12],"through":[13],"embedded":[14],"instrumentation":[15,21],"FPGAs":[17],"and":[18],"presents":[19],"new":[20],"that":[22],"allows":[23],"any":[24],"cover":[25],"point":[26],"to":[27],"be":[28],"measured.":[29]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
