{"id":"https://openalex.org/W2061007021","doi":"https://doi.org/10.1109/mdat.2013.2249555","title":"A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay","display_name":"A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay","publication_year":2013,"publication_date":"2013-04-01","ids":{"openalex":"https://openalex.org/W2061007021","doi":"https://doi.org/10.1109/mdat.2013.2249555","mag":"2061007021"},"language":"en","primary_location":{"id":"doi:10.1109/mdat.2013.2249555","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2013.2249555","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101154831","display_name":"Kan Xiao","orcid":null},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kan Xiao","raw_affiliation_strings":["Computer engineering, University of Connecticut, Storrs, USA","ECE Department University of Connecticut Storrs, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer engineering, University of Connecticut, Storrs, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"ECE Department University of Connecticut Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100632100","display_name":"Xuehui Zhang","orcid":"https://orcid.org/0000-0001-5348-4959"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xuehui Zhang","raw_affiliation_strings":["ECE Department, University of Connecticut, USA","ECE Department University of Connecticut Storrs, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ECE Department, University of Connecticut, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"ECE Department University of Connecticut Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113697198","display_name":"Mohammad Tehranipoor","orcid":null},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammad Tehranipoor","raw_affiliation_strings":["ECE Department, University of Connecticut, Storrs, CT, USA","ECE Department University of Connecticut Storrs, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ECE Department, University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"ECE Department University of Connecticut Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I140172145"],"apc_list":null,"apc_paid":null,"fwci":16.0551,"has_fulltext":false,"cited_by_count":100,"citation_normalized_percentile":{"value":0.99300907,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":"30","issue":"2","first_page":"26","last_page":"34"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9815000295639038,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6804621815681458},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6219515800476074},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5506040453910828},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5341777801513672},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5247502326965332},{"id":"https://openalex.org/keywords/hardware-trojan","display_name":"Hardware Trojan","score":0.5087223649024963},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4494955241680145},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4250980019569397},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3805626630783081},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.34802600741386414},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3333769142627716},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2808364927768707},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17914214730262756},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09341806173324585}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6804621815681458},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6219515800476074},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5506040453910828},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5341777801513672},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5247502326965332},{"id":"https://openalex.org/C2780873074","wikidata":"https://www.wikidata.org/wiki/Q5656397","display_name":"Hardware Trojan","level":3,"score":0.5087223649024963},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4494955241680145},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4250980019569397},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3805626630783081},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.34802600741386414},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3333769142627716},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2808364927768707},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17914214730262756},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09341806173324585}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mdat.2013.2249555","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mdat.2013.2249555","pdf_url":null,"source":{"id":"https://openalex.org/S4210176427","display_name":"IEEE Design and Test","issn_l":"2168-2356","issn":["2168-2356","2168-2364"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2012032225","https://openalex.org/W2040851326","https://openalex.org/W2098536553","https://openalex.org/W2106366482","https://openalex.org/W2109894721","https://openalex.org/W2112705672","https://openalex.org/W2145937629","https://openalex.org/W2150928734","https://openalex.org/W2157977768","https://openalex.org/W2161998562","https://openalex.org/W2172075479","https://openalex.org/W3099839986","https://openalex.org/W3150167865","https://openalex.org/W4205380271","https://openalex.org/W6676710984","https://openalex.org/W6682184091","https://openalex.org/W6685194180"],"related_works":["https://openalex.org/W2052455055","https://openalex.org/W4386968318","https://openalex.org/W2090237663","https://openalex.org/W2147595938","https://openalex.org/W4232628459","https://openalex.org/W2377749234","https://openalex.org/W853533475","https://openalex.org/W4308823727","https://openalex.org/W1506442459","https://openalex.org/W1572462408"],"abstract_inverted_index":{"Clock":[0],"sweeping":[1],"can":[2],"be":[3],"used":[4],"to":[5],"generate":[6],"signatures":[7],"for":[8,37],"the":[9,16,26],"purpose":[10],"of":[11,18,28],"detecting":[12],"hardware":[13],"Trojans.":[14],"With":[15],"help":[17],"simulations":[19],"and":[20],"FPGA":[21],"results,":[22],"this":[23],"article":[24],"demonstrates":[25],"effectiveness":[27],"their":[29],"proposed":[30],"clock-sweeping":[31],"technique":[32],"under":[33],"process":[34],"variations,":[35],"even":[36],"Trojans":[38],"as":[39,41],"small":[40],"a":[42],"few":[43],"gates.":[44]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":15},{"year":2020,"cited_by_count":11},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":16},{"year":2016,"cited_by_count":8},{"year":2015,"cited_by_count":14},{"year":2014,"cited_by_count":9}],"updated_date":"2026-07-25T09:21:30.201066","created_date":"2025-10-10T00:00:00"}